| /Linux-v4.19/drivers/net/wireless/quantenna/qtnfmac/pearl/ |
| D | pcie_regs_pearl.h | 26 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
27 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
28 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) argument
29 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14) argument
30 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18) argument
31 #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c) argument
32 #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20) argument
33 #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24) argument
34 #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28) argument
35 #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c) argument
[all …]
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| /Linux-v4.19/drivers/clk/imx/ |
| D | clk-imx7d.c | 406 void __iomem *base; in imx7d_clocks_init() local
414 base = of_iomap(np, 0); in imx7d_clocks_init()
415 WARN_ON(!base); in imx7d_clocks_init()
417 …clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src… in imx7d_clocks_init()
418 …clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_sr… in imx7d_clocks_init()
419 …clks[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src… in imx7d_clocks_init()
420 …clks[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_sr… in imx7d_clocks_init()
421 …clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_… in imx7d_clocks_init()
422 …clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass… in imx7d_clocks_init()
424 clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f); in imx7d_clocks_init()
[all …]
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| D | clk-imx6sll.c | 82 void __iomem *base; in imx6sll_clocks_init() local
94 base = of_iomap(np, 0); in imx6sll_clocks_init()
96 WARN_ON(!base); in imx6sll_clocks_init()
99 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
100 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
101 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
102 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
103 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); in imx6sll_clocks_init()
104 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); in imx6sll_clocks_init()
105 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0)); in imx6sll_clocks_init()
[all …]
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| D | clk-imx6ul.c | 125 void __iomem *base; in imx6ul_clocks_init() local
137 base = of_iomap(np, 0); in imx6ul_clocks_init()
139 WARN_ON(!base); in imx6ul_clocks_init()
141 …clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
142 …clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
143 …clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
144 …clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
145 …clks[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
146 …clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
147 …clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
[all …]
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| D | clk-imx6sx.c | 136 void __iomem *base; in imx6sx_clocks_init() local
152 base = of_iomap(np, 0); in imx6sx_clocks_init()
153 WARN_ON(!base); in imx6sx_clocks_init()
155 …clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
156 …clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
157 …clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
158 …clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
159 …clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
160 …clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
161 …clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
[all …]
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| D | clk-imx6sl.c | 193 void __iomem *base; in imx6sl_clocks_init() local
203 base = of_iomap(np, 0); in imx6sl_clocks_init()
204 WARN_ON(!base); in imx6sl_clocks_init()
205 anatop_base = base; in imx6sl_clocks_init()
207 …clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
208 …clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
209 …clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
210 …clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
211 …clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
212 …clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
[all …]
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| D | clk-imx6q.c | 413 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
425 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
426 WARN_ON(!base); in imx6q_clocks_init()
436 …clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
437 …clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
438 …clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
439 …clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
440 …clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
441 …clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
442 …clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
[all …]
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| /Linux-v4.19/drivers/scsi/ |
| D | aha1740.h | 19 #define HID0(base) (base + 0x0) argument
20 #define HID1(base) (base + 0x1) argument
21 #define HID2(base) (base + 0x2) argument
22 #define HID3(base) (base + 0x3) argument
23 #define EBCNTRL(base) (base + 0x4) argument
24 #define PORTADR(base) (base + 0x40) argument
25 #define BIOSADR(base) (base + 0x41) argument
26 #define INTDEF(base) (base + 0x42) argument
27 #define SCSIDEF(base) (base + 0x43) argument
28 #define BUSDEF(base) (base + 0x44) argument
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| D | nsp32_io.h | 12 static inline void nsp32_write1(unsigned int base, in nsp32_write1() argument
16 outb(val, (base + index)); in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1() argument
22 return inb(base + index); in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2() argument
29 outw(val, (base + index)); in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2() argument
35 return inw(base + index); in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4() argument
42 outl(val, (base + index)); in nsp32_write4()
[all …]
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| /Linux-v4.19/drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi5_core.c | 51 void __iomem *base = core->base; in hdmi_core_ddc_init() local
66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
67 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi_core_ddc_init()
72 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
76 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
78 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
83 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
85 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
90 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
92 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
[all …]
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| /Linux-v4.19/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_28nm_8960.c | 20 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
22 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
28 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
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| D | dsi_phy_28nm.c | 20 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
22 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
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| D | dsi_phy_20nm.c | 20 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing() local
22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, in dsi_20nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, in dsi_20nm_dphy_set_timing()
[all …]
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| /Linux-v4.19/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi5_core.c | 52 void __iomem *base = core->base; in hdmi_core_ddc_init() local
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
68 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi_core_ddc_init()
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
77 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
84 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
91 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
[all …]
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| /Linux-v4.19/drivers/isdn/hardware/avm/ |
| D | avmcard.h | 219 static inline unsigned char b1outp(unsigned int base, in b1outp() argument
223 outb(value, base + offset); in b1outp()
224 return inb(base + B1_ANALYSE); in b1outp()
228 static inline int b1_rx_full(unsigned int base) in b1_rx_full() argument
230 return inb(base + B1_INSTAT) & 0x1; in b1_rx_full()
233 static inline unsigned char b1_get_byte(unsigned int base) in b1_get_byte() argument
236 while (!b1_rx_full(base) && time_before(jiffies, stop)); in b1_get_byte()
237 if (b1_rx_full(base)) in b1_get_byte()
238 return inb(base + B1_READ); in b1_get_byte()
239 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base); in b1_get_byte()
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| /Linux-v4.19/arch/mips/alchemy/common/ |
| D | usb.c | 97 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl() argument
101 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
102 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
111 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
117 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
122 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) in __au1300_ohci_control() argument
127 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
130 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
133 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
136 __au1300_usb_phyctl(base, enable); /* power up the PHYs */ in __au1300_ohci_control()
[all …]
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| /Linux-v4.19/drivers/media/platform/s5p-jpeg/ |
| D | jpeg-hw-exynos4.c | 19 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset() argument
23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
27 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
28 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
32 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
35 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode() argument
39 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
44 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
48 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
[all …]
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| /Linux-v4.19/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_fw_defs.h | 15 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
17 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
33 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
35 (IRO[323].base + ((pfId) * IRO[323].m1))
[all …]
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| /Linux-v4.19/drivers/s390/block/ |
| D | dasd_ioctl.c | 46 struct dasd_device *base; in dasd_ioctl_enable() local
51 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_enable()
52 if (!base) in dasd_ioctl_enable()
55 dasd_enable_device(base); in dasd_ioctl_enable()
59 (loff_t)get_capacity(base->block->gdp) << 9); in dasd_ioctl_enable()
61 dasd_put_device(base); in dasd_ioctl_enable()
72 struct dasd_device *base; in dasd_ioctl_disable() local
77 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_disable()
78 if (!base) in dasd_ioctl_disable()
88 dasd_set_target_state(base, DASD_STATE_BASIC); in dasd_ioctl_disable()
[all …]
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| /Linux-v4.19/drivers/phy/qualcomm/ |
| D | phy-qcom-apq8064-sata.c | 100 void __iomem *base = phy->mmio; in qcom_apq8064_sata_phy_init() local
104 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); in qcom_apq8064_sata_phy_init()
105 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
110 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
111 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); in qcom_apq8064_sata_phy_init()
112 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); in qcom_apq8064_sata_phy_init()
113 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); in qcom_apq8064_sata_phy_init()
114 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); in qcom_apq8064_sata_phy_init()
117 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); in qcom_apq8064_sata_phy_init()
118 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); in qcom_apq8064_sata_phy_init()
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| /Linux-v4.19/tools/testing/selftests/powerpc/primitives/asm/ |
| D | ppc_asm.h | 77 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) argument
78 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) argument
79 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) argument
80 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) argument
82 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) argument
83 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) argument
84 #define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base) argument
85 #define REST_NVGPRS(base) lmw 13, GPR0+4*13(base) argument
88 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) argument
89 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) argument
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| /Linux-v4.19/arch/powerpc/include/asm/ |
| D | ppc_asm.h | 77 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) argument
78 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) argument
79 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) argument
80 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) argument
82 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) argument
83 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) argument
84 #define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base) argument
85 #define REST_NVGPRS(base) lmw 13, GPR0+4*13(base) argument
88 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) argument
89 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) argument
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| /Linux-v4.19/arch/arm/plat-orion/ |
| D | pcie.c | 55 u32 orion_pcie_dev_id(void __iomem *base) in orion_pcie_dev_id() argument
57 return readl(base + PCIE_DEV_ID_OFF) >> 16; in orion_pcie_dev_id()
60 u32 orion_pcie_rev(void __iomem *base) in orion_pcie_rev() argument
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; in orion_pcie_rev()
65 int orion_pcie_link_up(void __iomem *base) in orion_pcie_link_up() argument
67 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); in orion_pcie_link_up()
70 int __init orion_pcie_x4_mode(void __iomem *base) in orion_pcie_x4_mode() argument
72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); in orion_pcie_x4_mode()
75 int orion_pcie_get_local_bus_nr(void __iomem *base) in orion_pcie_get_local_bus_nr() argument
77 u32 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_get_local_bus_nr()
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| /Linux-v4.19/drivers/gpio/ |
| D | gpio-winbond.c | 131 unsigned long base; member
142 static int winbond_sio_enter(unsigned long base) in winbond_sio_enter() argument
144 if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME)) in winbond_sio_enter()
151 outb(WB_SIO_EXT_ENTER_KEY, base); in winbond_sio_enter()
152 outb(WB_SIO_EXT_ENTER_KEY, base); in winbond_sio_enter()
157 static void winbond_sio_select_logical(unsigned long base, u8 dev) in winbond_sio_select_logical() argument
159 outb(WB_SIO_REG_LOGICAL, base); in winbond_sio_select_logical()
160 outb(dev, base + 1); in winbond_sio_select_logical()
163 static void winbond_sio_leave(unsigned long base) in winbond_sio_leave() argument
165 outb(WB_SIO_EXT_EXIT_KEY, base); in winbond_sio_leave()
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| /Linux-v4.19/include/linux/mmc/ |
| D | sh_mmcif.h | 97 static inline void sh_mmcif_boot_cmd_send(void __iomem *base, in sh_mmcif_boot_cmd_send() argument
100 sh_mmcif_writel(base, MMCIF_CE_INT, 0); in sh_mmcif_boot_cmd_send()
101 sh_mmcif_writel(base, MMCIF_CE_ARG, arg); in sh_mmcif_boot_cmd_send()
102 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); in sh_mmcif_boot_cmd_send()
105 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) in sh_mmcif_boot_cmd_poll() argument
111 tmp = sh_mmcif_readl(base, MMCIF_CE_INT); in sh_mmcif_boot_cmd_poll()
113 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask); in sh_mmcif_boot_cmd_poll()
121 static inline int sh_mmcif_boot_cmd(void __iomem *base, in sh_mmcif_boot_cmd() argument
124 sh_mmcif_boot_cmd_send(base, cmd, arg); in sh_mmcif_boot_cmd()
125 return sh_mmcif_boot_cmd_poll(base, 0x00010000); in sh_mmcif_boot_cmd()
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