1 /*
2 * R8A77995 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
16
17 #include <linux/kernel.h>
18
19 #include "core.h"
20 #include "sh_pfc.h"
21
22 #define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_9(0, fn, sfx), \
24 PORT_GP_32(1, fn, sfx), \
25 PORT_GP_32(2, fn, sfx), \
26 PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_32(4, fn, sfx), \
28 PORT_GP_21(5, fn, sfx), \
29 PORT_GP_14(6, fn, sfx)
30
31 /*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36 /* GPSR0 */
37 #define GPSR0_8 F_(MLB_SIG, IP0_27_24)
38 #define GPSR0_7 F_(MLB_DAT, IP0_23_20)
39 #define GPSR0_6 F_(MLB_CLK, IP0_19_16)
40 #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
41 #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
42 #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
43 #define GPSR0_2 F_(IRQ0_A, IP0_3_0)
44 #define GPSR0_1 FM(USB0_OVC)
45 #define GPSR0_0 FM(USB0_PWEN)
46
47 /* GPSR1 */
48 #define GPSR1_31 F_(QPOLB, IP4_27_24)
49 #define GPSR1_30 F_(QPOLA, IP4_23_20)
50 #define GPSR1_29 F_(DU_CDE, IP4_19_16)
51 #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
52 #define GPSR1_27 F_(DU_DISP, IP4_11_8)
53 #define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
54 #define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
55 #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
56 #define GPSR1_23 F_(DU_DR7, IP3_27_24)
57 #define GPSR1_22 F_(DU_DR6, IP3_23_20)
58 #define GPSR1_21 F_(DU_DR5, IP3_19_16)
59 #define GPSR1_20 F_(DU_DR4, IP3_15_12)
60 #define GPSR1_19 F_(DU_DR3, IP3_11_8)
61 #define GPSR1_18 F_(DU_DR2, IP3_7_4)
62 #define GPSR1_17 F_(DU_DR1, IP3_3_0)
63 #define GPSR1_16 F_(DU_DR0, IP2_31_28)
64 #define GPSR1_15 F_(DU_DG7, IP2_27_24)
65 #define GPSR1_14 F_(DU_DG6, IP2_23_20)
66 #define GPSR1_13 F_(DU_DG5, IP2_19_16)
67 #define GPSR1_12 F_(DU_DG4, IP2_15_12)
68 #define GPSR1_11 F_(DU_DG3, IP2_11_8)
69 #define GPSR1_10 F_(DU_DG2, IP2_7_4)
70 #define GPSR1_9 F_(DU_DG1, IP2_3_0)
71 #define GPSR1_8 F_(DU_DG0, IP1_31_28)
72 #define GPSR1_7 F_(DU_DB7, IP1_27_24)
73 #define GPSR1_6 F_(DU_DB6, IP1_23_20)
74 #define GPSR1_5 F_(DU_DB5, IP1_19_16)
75 #define GPSR1_4 F_(DU_DB4, IP1_15_12)
76 #define GPSR1_3 F_(DU_DB3, IP1_11_8)
77 #define GPSR1_2 F_(DU_DB2, IP1_7_4)
78 #define GPSR1_1 F_(DU_DB1, IP1_3_0)
79 #define GPSR1_0 F_(DU_DB0, IP0_31_28)
80
81 /* GPSR2 */
82 #define GPSR2_31 F_(NFCE_N, IP8_19_16)
83 #define GPSR2_30 F_(NFCLE, IP8_15_12)
84 #define GPSR2_29 F_(NFALE, IP8_11_8)
85 #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
86 #define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
87 #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
88 #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
89 #define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
90 #define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
91 #define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
92 #define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
93 #define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
94 #define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
95 #define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
96 #define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
97 #define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
98 #define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
99 #define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
100 #define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
101 #define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
102 #define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
103 #define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
104 #define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
105 #define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
106 #define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
107 #define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
108 #define GPSR2_5 FM(VI4_DATA4)
109 #define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
110 #define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
111 #define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
112 #define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
113 #define GPSR2_0 FM(VI4_CLK)
114
115 /* GPSR3 */
116 #define GPSR3_9 F_(NFDATA7, IP9_31_28)
117 #define GPSR3_8 F_(NFDATA6, IP9_27_24)
118 #define GPSR3_7 F_(NFDATA5, IP9_23_20)
119 #define GPSR3_6 F_(NFDATA4, IP9_19_16)
120 #define GPSR3_5 F_(NFDATA3, IP9_15_12)
121 #define GPSR3_4 F_(NFDATA2, IP9_11_8)
122 #define GPSR3_3 F_(NFDATA1, IP9_7_4)
123 #define GPSR3_2 F_(NFDATA0, IP9_3_0)
124 #define GPSR3_1 F_(NFWE_N, IP8_31_28)
125 #define GPSR3_0 F_(NFRE_N, IP8_27_24)
126
127 /* GPSR4 */
128 #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
129 #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
130 #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
131 #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
132 #define GPSR4_27 FM(TX2)
133 #define GPSR4_26 FM(RX2)
134 #define GPSR4_25 F_(SCK2, IP12_11_8)
135 #define GPSR4_24 F_(TX1_A, IP12_7_4)
136 #define GPSR4_23 F_(RX1_A, IP12_3_0)
137 #define GPSR4_22 F_(SCK1_A, IP11_31_28)
138 #define GPSR4_21 F_(TX0_A, IP11_27_24)
139 #define GPSR4_20 F_(RX0_A, IP11_23_20)
140 #define GPSR4_19 F_(SCK0_A, IP11_19_16)
141 #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
142 #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
143 #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
144 #define GPSR4_15 FM(MSIOF0_RXD)
145 #define GPSR4_14 FM(MSIOF0_TXD)
146 #define GPSR4_13 FM(MSIOF0_SYNC)
147 #define GPSR4_12 FM(MSIOF0_SCK)
148 #define GPSR4_11 F_(SDA1, IP11_3_0)
149 #define GPSR4_10 F_(SCL1, IP10_31_28)
150 #define GPSR4_9 FM(SDA0)
151 #define GPSR4_8 FM(SCL0)
152 #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
153 #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
154 #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
155 #define GPSR4_4 F_(SSI_WS34, IP10_15_12)
156 #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
157 #define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
158 #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
159 #define GPSR4_0 F_(NFRB_N, IP8_23_20)
160
161 /* GPSR5 */
162 #define GPSR5_20 FM(AVB0_LINK)
163 #define GPSR5_19 FM(AVB0_PHY_INT)
164 #define GPSR5_18 FM(AVB0_MAGIC)
165 #define GPSR5_17 FM(AVB0_MDC)
166 #define GPSR5_16 FM(AVB0_MDIO)
167 #define GPSR5_15 FM(AVB0_TXCREFCLK)
168 #define GPSR5_14 FM(AVB0_TD3)
169 #define GPSR5_13 FM(AVB0_TD2)
170 #define GPSR5_12 FM(AVB0_TD1)
171 #define GPSR5_11 FM(AVB0_TD0)
172 #define GPSR5_10 FM(AVB0_TXC)
173 #define GPSR5_9 FM(AVB0_TX_CTL)
174 #define GPSR5_8 FM(AVB0_RD3)
175 #define GPSR5_7 FM(AVB0_RD2)
176 #define GPSR5_6 FM(AVB0_RD1)
177 #define GPSR5_5 FM(AVB0_RD0)
178 #define GPSR5_4 FM(AVB0_RXC)
179 #define GPSR5_3 FM(AVB0_RX_CTL)
180 #define GPSR5_2 F_(CAN_CLK, IP12_23_20)
181 #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
182 #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
183
184 /* GPSR6 */
185 #define GPSR6_13 FM(RPC_INT_N)
186 #define GPSR6_12 FM(RPC_RESET_N)
187 #define GPSR6_11 FM(QSPI1_SSL)
188 #define GPSR6_10 FM(QSPI1_IO3)
189 #define GPSR6_9 FM(QSPI1_IO2)
190 #define GPSR6_8 FM(QSPI1_MISO_IO1)
191 #define GPSR6_7 FM(QSPI1_MOSI_IO0)
192 #define GPSR6_6 FM(QSPI1_SPCLK)
193 #define GPSR6_5 FM(QSPI0_SSL)
194 #define GPSR6_4 FM(QSPI0_IO3)
195 #define GPSR6_3 FM(QSPI0_IO2)
196 #define GPSR6_2 FM(QSPI0_MISO_IO1)
197 #define GPSR6_1 FM(QSPI0_MOSI_IO0)
198 #define GPSR6_0 FM(QSPI0_SPCLK)
199
200 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
201 #define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233
234 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
235 #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267
268 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
269 #define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301
302 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
303 #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313
314 #define PINMUX_GPSR \
315 \
316 GPSR1_31 GPSR2_31 GPSR4_31 \
317 GPSR1_30 GPSR2_30 GPSR4_30 \
318 GPSR1_29 GPSR2_29 GPSR4_29 \
319 GPSR1_28 GPSR2_28 GPSR4_28 \
320 GPSR1_27 GPSR2_27 GPSR4_27 \
321 GPSR1_26 GPSR2_26 GPSR4_26 \
322 GPSR1_25 GPSR2_25 GPSR4_25 \
323 GPSR1_24 GPSR2_24 GPSR4_24 \
324 GPSR1_23 GPSR2_23 GPSR4_23 \
325 GPSR1_22 GPSR2_22 GPSR4_22 \
326 GPSR1_21 GPSR2_21 GPSR4_21 \
327 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
328 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
329 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
330 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
331 GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
332 GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
333 GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
334 GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
335 GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
336 GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
337 GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
338 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
339 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
340 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
341 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
342 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
343 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
344 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
345 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
346 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
347 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
348
349 #define PINMUX_IPSR \
350 \
351 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
352 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
353 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
354 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
355 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
356 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
357 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
358 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
359 \
360 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
361 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
362 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
363 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
364 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
365 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
366 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
367 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
368 \
369 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
370 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
371 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
372 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
373 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
374 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
375 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
376 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
377 \
378 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
379 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
380 FM(IP12_11_8) IP12_11_8 \
381 FM(IP12_15_12) IP12_15_12 \
382 FM(IP12_19_16) IP12_19_16 \
383 FM(IP12_23_20) IP12_23_20 \
384 FM(IP12_27_24) IP12_27_24 \
385 FM(IP12_31_28) IP12_31_28 \
386
387 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
388 #define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
389 #define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
390 #define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
391 #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
392 #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
393 #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
394 #define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
395 #define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
396 #define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
397 #define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
398 #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
399 #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
400 #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
401 #define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
402 #define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
403 #define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
404 #define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
405 #define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
406 #define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
407 #define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
408 #define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
409 #define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
410
411 #define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
412 #define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
413 #define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
414 #define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
415 #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
416 #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
417
418
419 #define PINMUX_MOD_SELS \
420 \
421 MOD_SEL1_31 \
422 MOD_SEL0_30 MOD_SEL1_30 \
423 MOD_SEL0_29 MOD_SEL1_29 \
424 MOD_SEL0_28 MOD_SEL1_28 \
425 MOD_SEL0_27 MOD_SEL1_27 \
426 MOD_SEL0_26 MOD_SEL1_26 \
427 MOD_SEL0_25 \
428 MOD_SEL0_24_23 \
429 MOD_SEL0_22_21 \
430 MOD_SEL0_20_19 \
431 MOD_SEL0_18_17 \
432 MOD_SEL0_15 \
433 MOD_SEL0_14 \
434 MOD_SEL0_13 \
435 MOD_SEL0_12 \
436 MOD_SEL0_11 \
437 MOD_SEL0_10 \
438 MOD_SEL0_5 \
439 MOD_SEL0_4 \
440 MOD_SEL0_3 \
441 MOD_SEL0_2 \
442 MOD_SEL0_1 \
443 MOD_SEL0_0
444
445 enum {
446 PINMUX_RESERVED = 0,
447
448 PINMUX_DATA_BEGIN,
449 GP_ALL(DATA),
450 PINMUX_DATA_END,
451
452 #define F_(x, y)
453 #define FM(x) FN_##x,
454 PINMUX_FUNCTION_BEGIN,
455 GP_ALL(FN),
456 PINMUX_GPSR
457 PINMUX_IPSR
458 PINMUX_MOD_SELS
459 PINMUX_FUNCTION_END,
460 #undef F_
461 #undef FM
462
463 #define F_(x, y)
464 #define FM(x) x##_MARK,
465 PINMUX_MARK_BEGIN,
466 PINMUX_GPSR
467 PINMUX_IPSR
468 PINMUX_MOD_SELS
469 PINMUX_MARK_END,
470 #undef F_
471 #undef FM
472 };
473
474 #define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
475 PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
476
477 #define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
478 PINMUX_DATA(fn##_MARK, FN_##msel)
479
480 static const u16 pinmux_data[] = {
481 PINMUX_DATA_GP_ALL(),
482
483 PINMUX_SINGLE(USB0_OVC),
484 PINMUX_SINGLE(USB0_PWEN),
485 PINMUX_SINGLE(VI4_DATA4),
486 PINMUX_SINGLE(VI4_CLK),
487 PINMUX_SINGLE(TX2),
488 PINMUX_SINGLE(RX2),
489 PINMUX_SINGLE(AVB0_LINK),
490 PINMUX_SINGLE(AVB0_PHY_INT),
491 PINMUX_SINGLE(AVB0_MAGIC),
492 PINMUX_SINGLE(AVB0_MDC),
493 PINMUX_SINGLE(AVB0_MDIO),
494 PINMUX_SINGLE(AVB0_TXCREFCLK),
495 PINMUX_SINGLE(AVB0_TD3),
496 PINMUX_SINGLE(AVB0_TD2),
497 PINMUX_SINGLE(AVB0_TD1),
498 PINMUX_SINGLE(AVB0_TD0),
499 PINMUX_SINGLE(AVB0_TXC),
500 PINMUX_SINGLE(AVB0_TX_CTL),
501 PINMUX_SINGLE(AVB0_RD3),
502 PINMUX_SINGLE(AVB0_RD2),
503 PINMUX_SINGLE(AVB0_RD1),
504 PINMUX_SINGLE(AVB0_RD0),
505 PINMUX_SINGLE(AVB0_RXC),
506 PINMUX_SINGLE(AVB0_RX_CTL),
507 PINMUX_SINGLE(RPC_INT_N),
508 PINMUX_SINGLE(RPC_RESET_N),
509 PINMUX_SINGLE(QSPI1_SSL),
510 PINMUX_SINGLE(QSPI1_IO3),
511 PINMUX_SINGLE(QSPI1_IO2),
512 PINMUX_SINGLE(QSPI1_MISO_IO1),
513 PINMUX_SINGLE(QSPI1_MOSI_IO0),
514 PINMUX_SINGLE(QSPI1_SPCLK),
515 PINMUX_SINGLE(QSPI0_SSL),
516 PINMUX_SINGLE(QSPI0_IO3),
517 PINMUX_SINGLE(QSPI0_IO2),
518 PINMUX_SINGLE(QSPI0_MISO_IO1),
519 PINMUX_SINGLE(QSPI0_MOSI_IO0),
520 PINMUX_SINGLE(QSPI0_SPCLK),
521 PINMUX_SINGLE(SCL0),
522 PINMUX_SINGLE(SDA0),
523
524 /* IPSR0 */
525 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
526 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
527
528 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
529
530 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
531 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
532
533 PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
534 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
535
536 PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
537 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
538 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
539
540 PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
541 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
542 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
543 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
544
545 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
546 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
547 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
548 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
549
550 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
551 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
552 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
553
554 /* IPSR1 */
555 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
556 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
557 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
558
559 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
560 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
561 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
562
563 PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
564 PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
565 PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
566
567 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
568 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
569 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
570
571 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
572 PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
573 PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
574
575 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
576 PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
577 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
578
579 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
580 PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
581 PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
582
583 PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
584 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
585 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
586
587 /* IPSR2 */
588 PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
589 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
590 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
591
592 PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
593 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
594
595 PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
596 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
597 PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
598
599 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
600 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
601 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
602
603 PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
604 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
605 PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
606
607 PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
608 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
609 PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
610
611 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
612 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
613 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
614
615 PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
616 PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
617 PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
618
619 /* IPSR3 */
620 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
621 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
622 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
623
624 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
625 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
626 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
627
628 PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
629 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
630 PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
631
632 PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
633 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
634 PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
635
636 PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
637 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
638 PINMUX_IPSR_GPSR(IP3_19_16, NMI),
639
640 PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
641 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
642 PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
643
644 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
645 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
646 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
647
648 PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
649 PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
650
651 /* IPSR4 */
652 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
653 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
654 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
655
656 PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
657 PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
658 PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
659
660 PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
661 PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
662 PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
663
664 PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
665 PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
666 PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
667 PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
668
669 PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
670 PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
671 PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
672
673 PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
674 PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
675
676 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
677 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
678
679 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
680 PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
681
682 /* IPSR5 */
683 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
684 PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
685
686 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
687 PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
688
689 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
690 PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
691
692 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
693 PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
694
695 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
696 PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
697
698 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
699 PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
700
701 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
702
703 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
704 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
705 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
706
707 /* IPSR6 */
708 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
709 PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
710
711 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
712 PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
713
714 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
715 PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
716
717 PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
718 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
719 PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
720
721 PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
722 PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
723 PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
724
725 PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
726 PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
727
728 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
729 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
730
731 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
732 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
733
734 /* IPSR7 */
735 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
736 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
737
738 PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
739 PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
740 PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
741
742 PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
743 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
744 PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
745
746 PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
747 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
748
749 PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
750 PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
751 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
752
753 PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
754 PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
755 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
756
757 PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
758
759 PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
760 PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
761 PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
762
763 PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
764 PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
765 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
766
767 /* IPSR8 */
768 PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
769 PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
770 PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
771 PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
772 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
773
774 PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
775 PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
776 PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
777 PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
778
779 PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
780 PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
781 PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
782 PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
783
784 PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
785 PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
786 PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
787 PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
788
789 PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
790 PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
791 PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
792
793 PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
794 PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
795 PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
796
797 PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
798 PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
799
800 PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
801 PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
802
803 /* IPSR9 */
804 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
805 PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
806
807 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
808 PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
809
810 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
811 PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
812
813 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
814 PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
815
816 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
817 PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
818
819 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
820 PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
821
822 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
823 PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
824
825 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
826 PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
827
828 /* IPSR10 */
829 PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
830 PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
831
832 PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
833 PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
834
835 PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
836 PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
837
838 PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
839 PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
840
841 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
842 PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
843 PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
844 PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
845 PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
846
847 PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
848 PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
849 PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
850 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
851
852 PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
853 PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
854 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
855 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
856
857 PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
858 PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
859
860 /* IPSR11 */
861 PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
862 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
863
864 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
865 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
866
867 PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
868 PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
869
870 PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
871 PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
872
873 PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
874 PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
875 PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
876
877 PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
878 PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
879 PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
880
881 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
882 PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
883 PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
884
885 PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
886 PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
887 PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
888 PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
889 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
890
891 /* IPSR12 */
892 PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
893 PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
894 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
895
896 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
897 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
898 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
899
900 PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
901 PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
902 PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
903
904 PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
905 PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
906 PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
907
908 PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
909 PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
910 PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
911
912 PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
913 PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
914 PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
915 PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
916
917 PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
918 PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
919 PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
920
921 PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
922 PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
923 PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
924
925 /* IPSR13 */
926 PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
927 PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
928 PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
929
930 PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
931 PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
932 PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
933 };
934
935 static const struct sh_pfc_pin pinmux_pins[] = {
936 PINMUX_GPIO_GP_ALL(),
937 };
938
939 /* - AUDIO CLOCK ------------------------------------------------------------- */
940 static const unsigned int audio_clk_a_pins[] = {
941 /* CLK A */
942 RCAR_GP_PIN(4, 1),
943 };
944 static const unsigned int audio_clk_a_mux[] = {
945 AUDIO_CLKA_MARK,
946 };
947 static const unsigned int audio_clk_b_pins[] = {
948 /* CLK B */
949 RCAR_GP_PIN(2, 27),
950 };
951 static const unsigned int audio_clk_b_mux[] = {
952 AUDIO_CLKB_MARK,
953 };
954 static const unsigned int audio_clkout_pins[] = {
955 /* CLKOUT */
956 RCAR_GP_PIN(4, 5),
957 };
958 static const unsigned int audio_clkout_mux[] = {
959 AUDIO_CLKOUT_MARK,
960 };
961 static const unsigned int audio_clkout1_pins[] = {
962 /* CLKOUT1 */
963 RCAR_GP_PIN(4, 22),
964 };
965 static const unsigned int audio_clkout1_mux[] = {
966 AUDIO_CLKOUT1_MARK,
967 };
968
969 /* - EtherAVB --------------------------------------------------------------- */
970 static const unsigned int avb0_link_pins[] = {
971 /* AVB0_LINK */
972 RCAR_GP_PIN(5, 20),
973 };
974 static const unsigned int avb0_link_mux[] = {
975 AVB0_LINK_MARK,
976 };
977 static const unsigned int avb0_magic_pins[] = {
978 /* AVB0_MAGIC */
979 RCAR_GP_PIN(5, 18),
980 };
981 static const unsigned int avb0_magic_mux[] = {
982 AVB0_MAGIC_MARK,
983 };
984 static const unsigned int avb0_phy_int_pins[] = {
985 /* AVB0_PHY_INT */
986 RCAR_GP_PIN(5, 19),
987 };
988 static const unsigned int avb0_phy_int_mux[] = {
989 AVB0_PHY_INT_MARK,
990 };
991 static const unsigned int avb0_mdio_pins[] = {
992 /* AVB0_MDC, AVB0_MDIO */
993 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
994 };
995 static const unsigned int avb0_mdio_mux[] = {
996 AVB0_MDC_MARK, AVB0_MDIO_MARK,
997 };
998 static const unsigned int avb0_mii_pins[] = {
999 /*
1000 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
1001 * AVB0_TD1, AVB0_TD2, AVB0_TD3,
1002 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
1003 * AVB0_RD1, AVB0_RD2, AVB0_RD3,
1004 * AVB0_TXCREFCLK
1005 */
1006 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1007 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1008 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1009 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1010 RCAR_GP_PIN(5, 15),
1011 };
1012 static const unsigned int avb0_mii_mux[] = {
1013 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
1014 AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1015 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
1016 AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1017 AVB0_TXCREFCLK_MARK,
1018 };
1019 static const unsigned int avb0_avtp_pps_a_pins[] = {
1020 /* AVB0_AVTP_PPS_A */
1021 RCAR_GP_PIN(5, 2),
1022 };
1023 static const unsigned int avb0_avtp_pps_a_mux[] = {
1024 AVB0_AVTP_PPS_A_MARK,
1025 };
1026 static const unsigned int avb0_avtp_match_a_pins[] = {
1027 /* AVB0_AVTP_MATCH_A */
1028 RCAR_GP_PIN(5, 1),
1029 };
1030 static const unsigned int avb0_avtp_match_a_mux[] = {
1031 AVB0_AVTP_MATCH_A_MARK,
1032 };
1033 static const unsigned int avb0_avtp_capture_a_pins[] = {
1034 /* AVB0_AVTP_CAPTURE_A */
1035 RCAR_GP_PIN(5, 0),
1036 };
1037 static const unsigned int avb0_avtp_capture_a_mux[] = {
1038 AVB0_AVTP_CAPTURE_A_MARK,
1039 };
1040 static const unsigned int avb0_avtp_pps_b_pins[] = {
1041 /* AVB0_AVTP_PPS_B */
1042 RCAR_GP_PIN(4, 16),
1043 };
1044 static const unsigned int avb0_avtp_pps_b_mux[] = {
1045 AVB0_AVTP_PPS_B_MARK,
1046 };
1047 static const unsigned int avb0_avtp_match_b_pins[] = {
1048 /* AVB0_AVTP_MATCH_B */
1049 RCAR_GP_PIN(4, 18),
1050 };
1051 static const unsigned int avb0_avtp_match_b_mux[] = {
1052 AVB0_AVTP_MATCH_B_MARK,
1053 };
1054 static const unsigned int avb0_avtp_capture_b_pins[] = {
1055 /* AVB0_AVTP_CAPTURE_B */
1056 RCAR_GP_PIN(4, 17),
1057 };
1058 static const unsigned int avb0_avtp_capture_b_mux[] = {
1059 AVB0_AVTP_CAPTURE_B_MARK,
1060 };
1061
1062 /* - CAN ------------------------------------------------------------------ */
1063 static const unsigned int can0_data_a_pins[] = {
1064 /* TX, RX */
1065 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1066 };
1067 static const unsigned int can0_data_a_mux[] = {
1068 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1069 };
1070 static const unsigned int can0_data_b_pins[] = {
1071 /* TX, RX */
1072 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
1073 };
1074 static const unsigned int can0_data_b_mux[] = {
1075 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1076 };
1077 static const unsigned int can1_data_a_pins[] = {
1078 /* TX, RX */
1079 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1080 };
1081 static const unsigned int can1_data_a_mux[] = {
1082 CAN1_TX_A_MARK, CAN1_RX_A_MARK,
1083 };
1084 static const unsigned int can1_data_b_pins[] = {
1085 /* TX, RX */
1086 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
1087 };
1088 static const unsigned int can1_data_b_mux[] = {
1089 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1090 };
1091
1092 /* - CAN Clock -------------------------------------------------------------- */
1093 static const unsigned int can_clk_pins[] = {
1094 /* CLK */
1095 RCAR_GP_PIN(5, 2),
1096 };
1097 static const unsigned int can_clk_mux[] = {
1098 CAN_CLK_MARK,
1099 };
1100
1101 /* - CAN FD ----------------------------------------------------------------- */
1102 static const unsigned int canfd0_data_pins[] = {
1103 /* TX, RX */
1104 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1105 };
1106 static const unsigned int canfd0_data_mux[] = {
1107 CANFD0_TX_MARK, CANFD0_RX_MARK,
1108 };
1109 static const unsigned int canfd1_data_pins[] = {
1110 /* TX, RX */
1111 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1112 };
1113 static const unsigned int canfd1_data_mux[] = {
1114 CANFD1_TX_MARK, CANFD1_RX_MARK,
1115 };
1116
1117 /* - DU --------------------------------------------------------------------- */
1118 static const unsigned int du_rgb666_pins[] = {
1119 /* R[7:2], G[7:2], B[7:2] */
1120 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1121 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1122 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1123 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1124 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1125 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1126 };
1127 static const unsigned int du_rgb666_mux[] = {
1128 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1129 DU_DR3_MARK, DU_DR2_MARK,
1130 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1131 DU_DG3_MARK, DU_DG2_MARK,
1132 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1133 DU_DB3_MARK, DU_DB2_MARK,
1134 };
1135 static const unsigned int du_rgb888_pins[] = {
1136 /* R[7:0], G[7:0], B[7:0] */
1137 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1138 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1139 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1140 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1141 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1142 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1143 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1144 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1145 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1146 };
1147 static const unsigned int du_rgb888_mux[] = {
1148 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1149 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1150 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1151 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1152 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1153 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1154 };
1155 static const unsigned int du_clk_in_1_pins[] = {
1156 /* CLKIN */
1157 RCAR_GP_PIN(1, 28),
1158 };
1159 static const unsigned int du_clk_in_1_mux[] = {
1160 DU_DOTCLKIN1_MARK
1161 };
1162 static const unsigned int du_clk_out_0_pins[] = {
1163 /* CLKOUT */
1164 RCAR_GP_PIN(1, 24),
1165 };
1166 static const unsigned int du_clk_out_0_mux[] = {
1167 DU_DOTCLKOUT0_MARK
1168 };
1169 static const unsigned int du_sync_pins[] = {
1170 /* VSYNC, HSYNC */
1171 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1172 };
1173 static const unsigned int du_sync_mux[] = {
1174 DU_VSYNC_MARK, DU_HSYNC_MARK
1175 };
1176 static const unsigned int du_disp_cde_pins[] = {
1177 /* DISP_CDE */
1178 RCAR_GP_PIN(1, 28),
1179 };
1180 static const unsigned int du_disp_cde_mux[] = {
1181 DU_DISP_CDE_MARK,
1182 };
1183 static const unsigned int du_cde_pins[] = {
1184 /* CDE */
1185 RCAR_GP_PIN(1, 29),
1186 };
1187 static const unsigned int du_cde_mux[] = {
1188 DU_CDE_MARK,
1189 };
1190 static const unsigned int du_disp_pins[] = {
1191 /* DISP */
1192 RCAR_GP_PIN(1, 27),
1193 };
1194 static const unsigned int du_disp_mux[] = {
1195 DU_DISP_MARK,
1196 };
1197
1198 /* - I2C -------------------------------------------------------------------- */
1199 static const unsigned int i2c0_pins[] = {
1200 /* SCL, SDA */
1201 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1202 };
1203 static const unsigned int i2c0_mux[] = {
1204 SCL0_MARK, SDA0_MARK,
1205 };
1206 static const unsigned int i2c1_pins[] = {
1207 /* SCL, SDA */
1208 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1209 };
1210 static const unsigned int i2c1_mux[] = {
1211 SCL1_MARK, SDA1_MARK,
1212 };
1213 static const unsigned int i2c2_a_pins[] = {
1214 /* SCL, SDA */
1215 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1216 };
1217 static const unsigned int i2c2_a_mux[] = {
1218 SCL2_A_MARK, SDA2_A_MARK,
1219 };
1220 static const unsigned int i2c2_b_pins[] = {
1221 /* SCL, SDA */
1222 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
1223 };
1224 static const unsigned int i2c2_b_mux[] = {
1225 SCL2_B_MARK, SDA2_B_MARK,
1226 };
1227 static const unsigned int i2c3_a_pins[] = {
1228 /* SCL, SDA */
1229 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1230 };
1231 static const unsigned int i2c3_a_mux[] = {
1232 SCL3_A_MARK, SDA3_A_MARK,
1233 };
1234 static const unsigned int i2c3_b_pins[] = {
1235 /* SCL, SDA */
1236 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1237 };
1238 static const unsigned int i2c3_b_mux[] = {
1239 SCL3_B_MARK, SDA3_B_MARK,
1240 };
1241
1242 /* - MMC ------------------------------------------------------------------- */
1243 static const unsigned int mmc_data1_pins[] = {
1244 /* D0 */
1245 RCAR_GP_PIN(3, 2),
1246 };
1247 static const unsigned int mmc_data1_mux[] = {
1248 MMC_D0_MARK,
1249 };
1250 static const unsigned int mmc_data4_pins[] = {
1251 /* D[0:3] */
1252 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1253 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1254 };
1255 static const unsigned int mmc_data4_mux[] = {
1256 MMC_D0_MARK, MMC_D1_MARK,
1257 MMC_D2_MARK, MMC_D3_MARK,
1258 };
1259 static const unsigned int mmc_data8_pins[] = {
1260 /* D[0:7] */
1261 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1262 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1263 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1264 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1265 };
1266 static const unsigned int mmc_data8_mux[] = {
1267 MMC_D0_MARK, MMC_D1_MARK,
1268 MMC_D2_MARK, MMC_D3_MARK,
1269 MMC_D4_MARK, MMC_D5_MARK,
1270 MMC_D6_MARK, MMC_D7_MARK,
1271 };
1272 static const unsigned int mmc_ctrl_pins[] = {
1273 /* CLK, CMD */
1274 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1275 };
1276 static const unsigned int mmc_ctrl_mux[] = {
1277 MMC_CLK_MARK, MMC_CMD_MARK,
1278 };
1279
1280 /* - PWM0 ------------------------------------------------------------------ */
1281 static const unsigned int pwm0_a_pins[] = {
1282 /* PWM */
1283 RCAR_GP_PIN(2, 1),
1284 };
1285
1286 static const unsigned int pwm0_a_mux[] = {
1287 PWM0_A_MARK,
1288 };
1289
1290 static const unsigned int pwm0_b_pins[] = {
1291 /* PWM */
1292 RCAR_GP_PIN(1, 18),
1293 };
1294
1295 static const unsigned int pwm0_b_mux[] = {
1296 PWM0_B_MARK,
1297 };
1298
1299 static const unsigned int pwm0_c_pins[] = {
1300 /* PWM */
1301 RCAR_GP_PIN(2, 29),
1302 };
1303
1304 static const unsigned int pwm0_c_mux[] = {
1305 PWM0_C_MARK,
1306 };
1307
1308 /* - PWM1 ------------------------------------------------------------------ */
1309 static const unsigned int pwm1_a_pins[] = {
1310 /* PWM */
1311 RCAR_GP_PIN(2, 2),
1312 };
1313
1314 static const unsigned int pwm1_a_mux[] = {
1315 PWM1_A_MARK,
1316 };
1317
1318 static const unsigned int pwm1_b_pins[] = {
1319 /* PWM */
1320 RCAR_GP_PIN(1, 19),
1321 };
1322
1323 static const unsigned int pwm1_b_mux[] = {
1324 PWM1_B_MARK,
1325 };
1326
1327 static const unsigned int pwm1_c_pins[] = {
1328 /* PWM */
1329 RCAR_GP_PIN(2, 30),
1330 };
1331
1332 static const unsigned int pwm1_c_mux[] = {
1333 PWM1_C_MARK,
1334 };
1335
1336 /* - PWM2 ------------------------------------------------------------------ */
1337 static const unsigned int pwm2_a_pins[] = {
1338 /* PWM */
1339 RCAR_GP_PIN(2, 3),
1340 };
1341
1342 static const unsigned int pwm2_a_mux[] = {
1343 PWM2_A_MARK,
1344 };
1345
1346 static const unsigned int pwm2_b_pins[] = {
1347 /* PWM */
1348 RCAR_GP_PIN(1, 22),
1349 };
1350
1351 static const unsigned int pwm2_b_mux[] = {
1352 PWM2_B_MARK,
1353 };
1354
1355 static const unsigned int pwm2_c_pins[] = {
1356 /* PWM */
1357 RCAR_GP_PIN(2, 31),
1358 };
1359
1360 static const unsigned int pwm2_c_mux[] = {
1361 PWM2_C_MARK,
1362 };
1363
1364 /* - PWM3 ------------------------------------------------------------------ */
1365 static const unsigned int pwm3_a_pins[] = {
1366 /* PWM */
1367 RCAR_GP_PIN(2, 4),
1368 };
1369
1370 static const unsigned int pwm3_a_mux[] = {
1371 PWM3_A_MARK,
1372 };
1373
1374 static const unsigned int pwm3_b_pins[] = {
1375 /* PWM */
1376 RCAR_GP_PIN(1, 27),
1377 };
1378
1379 static const unsigned int pwm3_b_mux[] = {
1380 PWM3_B_MARK,
1381 };
1382
1383 static const unsigned int pwm3_c_pins[] = {
1384 /* PWM */
1385 RCAR_GP_PIN(4, 0),
1386 };
1387
1388 static const unsigned int pwm3_c_mux[] = {
1389 PWM3_C_MARK,
1390 };
1391
1392 /* - SCIF0 ------------------------------------------------------------------ */
1393 static const unsigned int scif0_data_a_pins[] = {
1394 /* RX, TX */
1395 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1396 };
1397 static const unsigned int scif0_data_a_mux[] = {
1398 RX0_A_MARK, TX0_A_MARK,
1399 };
1400 static const unsigned int scif0_clk_a_pins[] = {
1401 /* SCK */
1402 RCAR_GP_PIN(4, 19),
1403 };
1404 static const unsigned int scif0_clk_a_mux[] = {
1405 SCK0_A_MARK,
1406 };
1407 static const unsigned int scif0_data_b_pins[] = {
1408 /* RX, TX */
1409 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
1410 };
1411 static const unsigned int scif0_data_b_mux[] = {
1412 RX0_B_MARK, TX0_B_MARK,
1413 };
1414 static const unsigned int scif0_clk_b_pins[] = {
1415 /* SCK */
1416 RCAR_GP_PIN(5, 2),
1417 };
1418 static const unsigned int scif0_clk_b_mux[] = {
1419 SCK0_B_MARK,
1420 };
1421 static const unsigned int scif0_ctrl_pins[] = {
1422 /* RTS, CTS */
1423 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1424 };
1425 static const unsigned int scif0_ctrl_mux[] = {
1426 RTS0_N_TANS_MARK, CTS0_N_MARK,
1427 };
1428 /* - SCIF1 ------------------------------------------------------------------ */
1429 static const unsigned int scif1_data_a_pins[] = {
1430 /* RX, TX */
1431 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
1432 };
1433 static const unsigned int scif1_data_a_mux[] = {
1434 RX1_A_MARK, TX1_A_MARK,
1435 };
1436 static const unsigned int scif1_clk_a_pins[] = {
1437 /* SCK */
1438 RCAR_GP_PIN(4, 22),
1439 };
1440 static const unsigned int scif1_clk_a_mux[] = {
1441 SCK1_A_MARK,
1442 };
1443 static const unsigned int scif1_data_b_pins[] = {
1444 /* RX, TX */
1445 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
1446 };
1447 static const unsigned int scif1_data_b_mux[] = {
1448 RX1_B_MARK, TX1_B_MARK,
1449 };
1450 static const unsigned int scif1_clk_b_pins[] = {
1451 /* SCK */
1452 RCAR_GP_PIN(2, 25),
1453 };
1454 static const unsigned int scif1_clk_b_mux[] = {
1455 SCK1_B_MARK,
1456 };
1457 static const unsigned int scif1_ctrl_pins[] = {
1458 /* RTS, CTS */
1459 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1460 };
1461 static const unsigned int scif1_ctrl_mux[] = {
1462 RTS1_N_TANS_MARK, CTS1_N_MARK,
1463 };
1464
1465 /* - SCIF2 ------------------------------------------------------------------ */
1466 static const unsigned int scif2_data_pins[] = {
1467 /* RX, TX */
1468 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
1469 };
1470 static const unsigned int scif2_data_mux[] = {
1471 RX2_MARK, TX2_MARK,
1472 };
1473 static const unsigned int scif2_clk_pins[] = {
1474 /* SCK */
1475 RCAR_GP_PIN(4, 25),
1476 };
1477 static const unsigned int scif2_clk_mux[] = {
1478 SCK2_MARK,
1479 };
1480 /* - SCIF3 ------------------------------------------------------------------ */
1481 static const unsigned int scif3_data_a_pins[] = {
1482 /* RX, TX */
1483 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
1484 };
1485 static const unsigned int scif3_data_a_mux[] = {
1486 RX3_A_MARK, TX3_A_MARK,
1487 };
1488 static const unsigned int scif3_clk_a_pins[] = {
1489 /* SCK */
1490 RCAR_GP_PIN(2, 30),
1491 };
1492 static const unsigned int scif3_clk_a_mux[] = {
1493 SCK3_A_MARK,
1494 };
1495 static const unsigned int scif3_data_b_pins[] = {
1496 /* RX, TX */
1497 RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
1498 };
1499 static const unsigned int scif3_data_b_mux[] = {
1500 RX3_B_MARK, TX3_B_MARK,
1501 };
1502 static const unsigned int scif3_clk_b_pins[] = {
1503 /* SCK */
1504 RCAR_GP_PIN(1, 29),
1505 };
1506 static const unsigned int scif3_clk_b_mux[] = {
1507 SCK3_B_MARK,
1508 };
1509 /* - SCIF4 ------------------------------------------------------------------ */
1510 static const unsigned int scif4_data_a_pins[] = {
1511 /* RX, TX */
1512 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1513 };
1514 static const unsigned int scif4_data_a_mux[] = {
1515 RX4_A_MARK, TX4_A_MARK,
1516 };
1517 static const unsigned int scif4_clk_a_pins[] = {
1518 /* SCK */
1519 RCAR_GP_PIN(2, 6),
1520 };
1521 static const unsigned int scif4_clk_a_mux[] = {
1522 SCK4_A_MARK,
1523 };
1524 static const unsigned int scif4_data_b_pins[] = {
1525 /* RX, TX */
1526 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1527 };
1528 static const unsigned int scif4_data_b_mux[] = {
1529 RX4_B_MARK, TX4_B_MARK,
1530 };
1531 static const unsigned int scif4_clk_b_pins[] = {
1532 /* SCK */
1533 RCAR_GP_PIN(1, 15),
1534 };
1535 static const unsigned int scif4_clk_b_mux[] = {
1536 SCK4_B_MARK,
1537 };
1538 /* - SCIF5 ------------------------------------------------------------------ */
1539 static const unsigned int scif5_data_a_pins[] = {
1540 /* RX, TX */
1541 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1542 };
1543 static const unsigned int scif5_data_a_mux[] = {
1544 RX5_A_MARK, TX5_A_MARK,
1545 };
1546 static const unsigned int scif5_clk_a_pins[] = {
1547 /* SCK */
1548 RCAR_GP_PIN(0, 6),
1549 };
1550 static const unsigned int scif5_clk_a_mux[] = {
1551 SCK5_A_MARK,
1552 };
1553 static const unsigned int scif5_data_b_pins[] = {
1554 /* RX, TX */
1555 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1556 };
1557 static const unsigned int scif5_data_b_mux[] = {
1558 RX5_B_MARK, TX5_B_MARK,
1559 };
1560 static const unsigned int scif5_clk_b_pins[] = {
1561 /* SCK */
1562 RCAR_GP_PIN(1, 3),
1563 };
1564 static const unsigned int scif5_clk_b_mux[] = {
1565 SCK5_B_MARK,
1566 };
1567 /* - SCIF Clock ------------------------------------------------------------- */
1568 static const unsigned int scif_clk_pins[] = {
1569 /* SCIF_CLK */
1570 RCAR_GP_PIN(2, 27),
1571 };
1572 static const unsigned int scif_clk_mux[] = {
1573 SCIF_CLK_MARK,
1574 };
1575
1576 /* - SSI ---------------------------------------------------------------*/
1577 static const unsigned int ssi3_data_pins[] = {
1578 /* SDATA */
1579 RCAR_GP_PIN(4, 3),
1580 };
1581 static const unsigned int ssi3_data_mux[] = {
1582 SSI_SDATA3_MARK,
1583 };
1584 static const unsigned int ssi34_ctrl_pins[] = {
1585 /* SCK, WS */
1586 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
1587 };
1588 static const unsigned int ssi34_ctrl_mux[] = {
1589 SSI_SCK34_MARK, SSI_WS34_MARK,
1590 };
1591 static const unsigned int ssi4_ctrl_a_pins[] = {
1592 /* SCK, WS */
1593 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1594 };
1595 static const unsigned int ssi4_ctrl_a_mux[] = {
1596 SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
1597 };
1598 static const unsigned int ssi4_data_a_pins[] = {
1599 /* SDATA */
1600 RCAR_GP_PIN(4, 6),
1601 };
1602 static const unsigned int ssi4_data_a_mux[] = {
1603 SSI_SDATA4_A_MARK,
1604 };
1605 static const unsigned int ssi4_ctrl_b_pins[] = {
1606 /* SCK, WS */
1607 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
1608 };
1609 static const unsigned int ssi4_ctrl_b_mux[] = {
1610 SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
1611 };
1612 static const unsigned int ssi4_data_b_pins[] = {
1613 /* SDATA */
1614 RCAR_GP_PIN(2, 16),
1615 };
1616 static const unsigned int ssi4_data_b_mux[] = {
1617 SSI_SDATA4_B_MARK,
1618 };
1619
1620 /* - USB0 ------------------------------------------------------------------- */
1621 static const unsigned int usb0_pins[] = {
1622 /* PWEN, OVC */
1623 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1624 };
1625 static const unsigned int usb0_mux[] = {
1626 USB0_PWEN_MARK, USB0_OVC_MARK,
1627 };
1628
1629 /* - VIN4 ------------------------------------------------------------------- */
1630 static const unsigned int vin4_data18_pins[] = {
1631 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1632 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1633 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1634 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1635 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1636 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1637 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1638 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1639 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1640 };
1641 static const unsigned int vin4_data18_mux[] = {
1642 VI4_DATA2_MARK, VI4_DATA3_MARK,
1643 VI4_DATA4_MARK, VI4_DATA5_MARK,
1644 VI4_DATA6_MARK, VI4_DATA7_MARK,
1645 VI4_DATA10_MARK, VI4_DATA11_MARK,
1646 VI4_DATA12_MARK, VI4_DATA13_MARK,
1647 VI4_DATA14_MARK, VI4_DATA15_MARK,
1648 VI4_DATA18_MARK, VI4_DATA19_MARK,
1649 VI4_DATA20_MARK, VI4_DATA21_MARK,
1650 VI4_DATA22_MARK, VI4_DATA23_MARK,
1651 };
1652 static const union vin_data vin4_data_pins = {
1653 .data24 = {
1654 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1655 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1656 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1657 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1658 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1659 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1660 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1661 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1662 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1663 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1664 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1665 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1666 },
1667 };
1668 static const union vin_data vin4_data_mux = {
1669 .data24 = {
1670 VI4_DATA0_MARK, VI4_DATA1_MARK,
1671 VI4_DATA2_MARK, VI4_DATA3_MARK,
1672 VI4_DATA4_MARK, VI4_DATA5_MARK,
1673 VI4_DATA6_MARK, VI4_DATA7_MARK,
1674 VI4_DATA8_MARK, VI4_DATA9_MARK,
1675 VI4_DATA10_MARK, VI4_DATA11_MARK,
1676 VI4_DATA12_MARK, VI4_DATA13_MARK,
1677 VI4_DATA14_MARK, VI4_DATA15_MARK,
1678 VI4_DATA16_MARK, VI4_DATA17_MARK,
1679 VI4_DATA18_MARK, VI4_DATA19_MARK,
1680 VI4_DATA20_MARK, VI4_DATA21_MARK,
1681 VI4_DATA22_MARK, VI4_DATA23_MARK,
1682 },
1683 };
1684 static const unsigned int vin4_sync_pins[] = {
1685 /* HSYNC#, VSYNC# */
1686 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1687 };
1688 static const unsigned int vin4_sync_mux[] = {
1689 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1690 };
1691 static const unsigned int vin4_field_pins[] = {
1692 /* FIELD */
1693 RCAR_GP_PIN(2, 27),
1694 };
1695 static const unsigned int vin4_field_mux[] = {
1696 VI4_FIELD_MARK,
1697 };
1698 static const unsigned int vin4_clkenb_pins[] = {
1699 /* CLKENB */
1700 RCAR_GP_PIN(2, 28),
1701 };
1702 static const unsigned int vin4_clkenb_mux[] = {
1703 VI4_CLKENB_MARK,
1704 };
1705 static const unsigned int vin4_clk_pins[] = {
1706 /* CLK */
1707 RCAR_GP_PIN(2, 0),
1708 };
1709 static const unsigned int vin4_clk_mux[] = {
1710 VI4_CLK_MARK,
1711 };
1712
1713 static const struct sh_pfc_pin_group pinmux_groups[] = {
1714 SH_PFC_PIN_GROUP(audio_clk_a),
1715 SH_PFC_PIN_GROUP(audio_clk_b),
1716 SH_PFC_PIN_GROUP(audio_clkout),
1717 SH_PFC_PIN_GROUP(audio_clkout1),
1718 SH_PFC_PIN_GROUP(avb0_link),
1719 SH_PFC_PIN_GROUP(avb0_magic),
1720 SH_PFC_PIN_GROUP(avb0_phy_int),
1721 SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
1722 SH_PFC_PIN_GROUP(avb0_mdio),
1723 SH_PFC_PIN_GROUP(avb0_mii),
1724 SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
1725 SH_PFC_PIN_GROUP(avb0_avtp_match_a),
1726 SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
1727 SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
1728 SH_PFC_PIN_GROUP(avb0_avtp_match_b),
1729 SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
1730 SH_PFC_PIN_GROUP(can0_data_a),
1731 SH_PFC_PIN_GROUP(can0_data_b),
1732 SH_PFC_PIN_GROUP(can1_data_a),
1733 SH_PFC_PIN_GROUP(can1_data_b),
1734 SH_PFC_PIN_GROUP(can_clk),
1735 SH_PFC_PIN_GROUP(canfd0_data),
1736 SH_PFC_PIN_GROUP(canfd1_data),
1737 SH_PFC_PIN_GROUP(du_rgb666),
1738 SH_PFC_PIN_GROUP(du_rgb888),
1739 SH_PFC_PIN_GROUP(du_clk_in_1),
1740 SH_PFC_PIN_GROUP(du_clk_out_0),
1741 SH_PFC_PIN_GROUP(du_sync),
1742 SH_PFC_PIN_GROUP(du_disp_cde),
1743 SH_PFC_PIN_GROUP(du_cde),
1744 SH_PFC_PIN_GROUP(du_disp),
1745 SH_PFC_PIN_GROUP(i2c0),
1746 SH_PFC_PIN_GROUP(i2c1),
1747 SH_PFC_PIN_GROUP(i2c2_a),
1748 SH_PFC_PIN_GROUP(i2c2_b),
1749 SH_PFC_PIN_GROUP(i2c3_a),
1750 SH_PFC_PIN_GROUP(i2c3_b),
1751 SH_PFC_PIN_GROUP(mmc_data1),
1752 SH_PFC_PIN_GROUP(mmc_data4),
1753 SH_PFC_PIN_GROUP(mmc_data8),
1754 SH_PFC_PIN_GROUP(mmc_ctrl),
1755 SH_PFC_PIN_GROUP(pwm0_a),
1756 SH_PFC_PIN_GROUP(pwm0_b),
1757 SH_PFC_PIN_GROUP(pwm0_c),
1758 SH_PFC_PIN_GROUP(pwm1_a),
1759 SH_PFC_PIN_GROUP(pwm1_b),
1760 SH_PFC_PIN_GROUP(pwm1_c),
1761 SH_PFC_PIN_GROUP(pwm2_a),
1762 SH_PFC_PIN_GROUP(pwm2_b),
1763 SH_PFC_PIN_GROUP(pwm2_c),
1764 SH_PFC_PIN_GROUP(pwm3_a),
1765 SH_PFC_PIN_GROUP(pwm3_b),
1766 SH_PFC_PIN_GROUP(pwm3_c),
1767 SH_PFC_PIN_GROUP(scif0_data_a),
1768 SH_PFC_PIN_GROUP(scif0_clk_a),
1769 SH_PFC_PIN_GROUP(scif0_data_b),
1770 SH_PFC_PIN_GROUP(scif0_clk_b),
1771 SH_PFC_PIN_GROUP(scif0_ctrl),
1772 SH_PFC_PIN_GROUP(scif1_data_a),
1773 SH_PFC_PIN_GROUP(scif1_clk_a),
1774 SH_PFC_PIN_GROUP(scif1_data_b),
1775 SH_PFC_PIN_GROUP(scif1_clk_b),
1776 SH_PFC_PIN_GROUP(scif1_ctrl),
1777 SH_PFC_PIN_GROUP(scif2_data),
1778 SH_PFC_PIN_GROUP(scif2_clk),
1779 SH_PFC_PIN_GROUP(scif3_data_a),
1780 SH_PFC_PIN_GROUP(scif3_clk_a),
1781 SH_PFC_PIN_GROUP(scif3_data_b),
1782 SH_PFC_PIN_GROUP(scif3_clk_b),
1783 SH_PFC_PIN_GROUP(scif4_data_a),
1784 SH_PFC_PIN_GROUP(scif4_clk_a),
1785 SH_PFC_PIN_GROUP(scif4_data_b),
1786 SH_PFC_PIN_GROUP(scif4_clk_b),
1787 SH_PFC_PIN_GROUP(scif5_data_a),
1788 SH_PFC_PIN_GROUP(scif5_clk_a),
1789 SH_PFC_PIN_GROUP(scif5_data_b),
1790 SH_PFC_PIN_GROUP(scif5_clk_b),
1791 SH_PFC_PIN_GROUP(scif_clk),
1792 SH_PFC_PIN_GROUP(ssi3_data),
1793 SH_PFC_PIN_GROUP(ssi34_ctrl),
1794 SH_PFC_PIN_GROUP(ssi4_ctrl_a),
1795 SH_PFC_PIN_GROUP(ssi4_data_a),
1796 SH_PFC_PIN_GROUP(ssi4_ctrl_b),
1797 SH_PFC_PIN_GROUP(ssi4_data_b),
1798 SH_PFC_PIN_GROUP(usb0),
1799 VIN_DATA_PIN_GROUP(vin4_data, 8),
1800 VIN_DATA_PIN_GROUP(vin4_data, 10),
1801 VIN_DATA_PIN_GROUP(vin4_data, 12),
1802 VIN_DATA_PIN_GROUP(vin4_data, 16),
1803 SH_PFC_PIN_GROUP(vin4_data18),
1804 VIN_DATA_PIN_GROUP(vin4_data, 20),
1805 VIN_DATA_PIN_GROUP(vin4_data, 24),
1806 SH_PFC_PIN_GROUP(vin4_sync),
1807 SH_PFC_PIN_GROUP(vin4_field),
1808 SH_PFC_PIN_GROUP(vin4_clkenb),
1809 SH_PFC_PIN_GROUP(vin4_clk),
1810 };
1811
1812 static const char * const audio_clk_groups[] = {
1813 "audio_clk_a",
1814 "audio_clk_b",
1815 "audio_clkout",
1816 "audio_clkout1",
1817 };
1818
1819 static const char * const avb0_groups[] = {
1820 "avb0_link",
1821 "avb0_magic",
1822 "avb0_phy_int",
1823 "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
1824 "avb0_mdio",
1825 "avb0_mii",
1826 "avb0_avtp_pps_a",
1827 "avb0_avtp_match_a",
1828 "avb0_avtp_capture_a",
1829 "avb0_avtp_pps_b",
1830 "avb0_avtp_match_b",
1831 "avb0_avtp_capture_b",
1832 };
1833
1834 static const char * const can0_groups[] = {
1835 "can0_data_a",
1836 "can0_data_b",
1837 };
1838 static const char * const can1_groups[] = {
1839 "can1_data_a",
1840 "can1_data_b",
1841 };
1842 static const char * const can_clk_groups[] = {
1843 "can_clk",
1844 };
1845
1846 static const char * const canfd0_groups[] = {
1847 "canfd0_data",
1848 };
1849 static const char * const canfd1_groups[] = {
1850 "canfd1_data",
1851 };
1852
1853 static const char * const du_groups[] = {
1854 "du_rgb666",
1855 "du_rgb888",
1856 "du_clk_in_1",
1857 "du_clk_out_0",
1858 "du_sync",
1859 "du_disp_cde",
1860 "du_cde",
1861 "du_disp",
1862 };
1863
1864 static const char * const i2c0_groups[] = {
1865 "i2c0",
1866 };
1867 static const char * const i2c1_groups[] = {
1868 "i2c1",
1869 };
1870
1871 static const char * const i2c2_groups[] = {
1872 "i2c2_a",
1873 "i2c2_b",
1874 };
1875
1876 static const char * const i2c3_groups[] = {
1877 "i2c3_a",
1878 "i2c3_b",
1879 };
1880
1881 static const char * const mmc_groups[] = {
1882 "mmc_data1",
1883 "mmc_data4",
1884 "mmc_data8",
1885 "mmc_ctrl",
1886 };
1887
1888 static const char * const pwm0_groups[] = {
1889 "pwm0_a",
1890 "pwm0_b",
1891 "pwm0_c",
1892 };
1893
1894 static const char * const pwm1_groups[] = {
1895 "pwm1_a",
1896 "pwm1_b",
1897 "pwm1_c",
1898 };
1899
1900 static const char * const pwm2_groups[] = {
1901 "pwm2_a",
1902 "pwm2_b",
1903 "pwm2_c",
1904 };
1905
1906 static const char * const pwm3_groups[] = {
1907 "pwm3_a",
1908 "pwm3_b",
1909 "pwm3_c",
1910 };
1911
1912 static const char * const scif0_groups[] = {
1913 "scif0_data_a",
1914 "scif0_clk_a",
1915 "scif0_data_b",
1916 "scif0_clk_b",
1917 "scif0_ctrl",
1918 };
1919
1920 static const char * const scif1_groups[] = {
1921 "scif1_data_a",
1922 "scif1_clk_a",
1923 "scif1_data_b",
1924 "scif1_clk_b",
1925 "scif1_ctrl",
1926 };
1927
1928 static const char * const scif2_groups[] = {
1929 "scif2_data",
1930 "scif2_clk",
1931 };
1932
1933 static const char * const scif3_groups[] = {
1934 "scif3_data_a",
1935 "scif3_clk_a",
1936 "scif3_data_b",
1937 "scif3_clk_b",
1938 };
1939
1940 static const char * const scif4_groups[] = {
1941 "scif4_data_a",
1942 "scif4_clk_a",
1943 "scif4_data_b",
1944 "scif4_clk_b",
1945 };
1946
1947 static const char * const scif5_groups[] = {
1948 "scif5_data_a",
1949 "scif5_clk_a",
1950 "scif5_data_b",
1951 "scif5_clk_b",
1952 };
1953
1954 static const char * const scif_clk_groups[] = {
1955 "scif_clk",
1956 };
1957
1958 static const char * const ssi_groups[] = {
1959 "ssi3_data",
1960 "ssi34_ctrl",
1961 "ssi4_ctrl_a",
1962 "ssi4_data_a",
1963 "ssi4_ctrl_b",
1964 "ssi4_data_b",
1965 };
1966
1967 static const char * const usb0_groups[] = {
1968 "usb0",
1969 };
1970
1971 static const char * const vin4_groups[] = {
1972 "vin4_data8",
1973 "vin4_data10",
1974 "vin4_data12",
1975 "vin4_data16",
1976 "vin4_data18",
1977 "vin4_data20",
1978 "vin4_data24",
1979 "vin4_sync",
1980 "vin4_field",
1981 "vin4_clkenb",
1982 "vin4_clk",
1983 };
1984
1985 static const struct sh_pfc_function pinmux_functions[] = {
1986 SH_PFC_FUNCTION(audio_clk),
1987 SH_PFC_FUNCTION(avb0),
1988 SH_PFC_FUNCTION(can0),
1989 SH_PFC_FUNCTION(can1),
1990 SH_PFC_FUNCTION(can_clk),
1991 SH_PFC_FUNCTION(canfd0),
1992 SH_PFC_FUNCTION(canfd1),
1993 SH_PFC_FUNCTION(du),
1994 SH_PFC_FUNCTION(i2c0),
1995 SH_PFC_FUNCTION(i2c1),
1996 SH_PFC_FUNCTION(i2c2),
1997 SH_PFC_FUNCTION(i2c3),
1998 SH_PFC_FUNCTION(mmc),
1999 SH_PFC_FUNCTION(pwm0),
2000 SH_PFC_FUNCTION(pwm1),
2001 SH_PFC_FUNCTION(pwm2),
2002 SH_PFC_FUNCTION(pwm3),
2003 SH_PFC_FUNCTION(scif0),
2004 SH_PFC_FUNCTION(scif1),
2005 SH_PFC_FUNCTION(scif2),
2006 SH_PFC_FUNCTION(scif3),
2007 SH_PFC_FUNCTION(scif4),
2008 SH_PFC_FUNCTION(scif5),
2009 SH_PFC_FUNCTION(scif_clk),
2010 SH_PFC_FUNCTION(ssi),
2011 SH_PFC_FUNCTION(usb0),
2012 SH_PFC_FUNCTION(vin4),
2013 };
2014
2015 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2016 #define F_(x, y) FN_##y
2017 #define FM(x) FN_##x
2018 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2019 0, 0,
2020 0, 0,
2021 0, 0,
2022 0, 0,
2023 0, 0,
2024 0, 0,
2025 0, 0,
2026 0, 0,
2027 0, 0,
2028 0, 0,
2029 0, 0,
2030 0, 0,
2031 0, 0,
2032 0, 0,
2033 0, 0,
2034 0, 0,
2035 0, 0,
2036 0, 0,
2037 0, 0,
2038 0, 0,
2039 0, 0,
2040 0, 0,
2041 0, 0,
2042 GP_0_8_FN, GPSR0_8,
2043 GP_0_7_FN, GPSR0_7,
2044 GP_0_6_FN, GPSR0_6,
2045 GP_0_5_FN, GPSR0_5,
2046 GP_0_4_FN, GPSR0_4,
2047 GP_0_3_FN, GPSR0_3,
2048 GP_0_2_FN, GPSR0_2,
2049 GP_0_1_FN, GPSR0_1,
2050 GP_0_0_FN, GPSR0_0, }
2051 },
2052 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2053 GP_1_31_FN, GPSR1_31,
2054 GP_1_30_FN, GPSR1_30,
2055 GP_1_29_FN, GPSR1_29,
2056 GP_1_28_FN, GPSR1_28,
2057 GP_1_27_FN, GPSR1_27,
2058 GP_1_26_FN, GPSR1_26,
2059 GP_1_25_FN, GPSR1_25,
2060 GP_1_24_FN, GPSR1_24,
2061 GP_1_23_FN, GPSR1_23,
2062 GP_1_22_FN, GPSR1_22,
2063 GP_1_21_FN, GPSR1_21,
2064 GP_1_20_FN, GPSR1_20,
2065 GP_1_19_FN, GPSR1_19,
2066 GP_1_18_FN, GPSR1_18,
2067 GP_1_17_FN, GPSR1_17,
2068 GP_1_16_FN, GPSR1_16,
2069 GP_1_15_FN, GPSR1_15,
2070 GP_1_14_FN, GPSR1_14,
2071 GP_1_13_FN, GPSR1_13,
2072 GP_1_12_FN, GPSR1_12,
2073 GP_1_11_FN, GPSR1_11,
2074 GP_1_10_FN, GPSR1_10,
2075 GP_1_9_FN, GPSR1_9,
2076 GP_1_8_FN, GPSR1_8,
2077 GP_1_7_FN, GPSR1_7,
2078 GP_1_6_FN, GPSR1_6,
2079 GP_1_5_FN, GPSR1_5,
2080 GP_1_4_FN, GPSR1_4,
2081 GP_1_3_FN, GPSR1_3,
2082 GP_1_2_FN, GPSR1_2,
2083 GP_1_1_FN, GPSR1_1,
2084 GP_1_0_FN, GPSR1_0, }
2085 },
2086 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2087 GP_2_31_FN, GPSR2_31,
2088 GP_2_30_FN, GPSR2_30,
2089 GP_2_29_FN, GPSR2_29,
2090 GP_2_28_FN, GPSR2_28,
2091 GP_2_27_FN, GPSR2_27,
2092 GP_2_26_FN, GPSR2_26,
2093 GP_2_25_FN, GPSR2_25,
2094 GP_2_24_FN, GPSR2_24,
2095 GP_2_23_FN, GPSR2_23,
2096 GP_2_22_FN, GPSR2_22,
2097 GP_2_21_FN, GPSR2_21,
2098 GP_2_20_FN, GPSR2_20,
2099 GP_2_19_FN, GPSR2_19,
2100 GP_2_18_FN, GPSR2_18,
2101 GP_2_17_FN, GPSR2_17,
2102 GP_2_16_FN, GPSR2_16,
2103 GP_2_15_FN, GPSR2_15,
2104 GP_2_14_FN, GPSR2_14,
2105 GP_2_13_FN, GPSR2_13,
2106 GP_2_12_FN, GPSR2_12,
2107 GP_2_11_FN, GPSR2_11,
2108 GP_2_10_FN, GPSR2_10,
2109 GP_2_9_FN, GPSR2_9,
2110 GP_2_8_FN, GPSR2_8,
2111 GP_2_7_FN, GPSR2_7,
2112 GP_2_6_FN, GPSR2_6,
2113 GP_2_5_FN, GPSR2_5,
2114 GP_2_4_FN, GPSR2_4,
2115 GP_2_3_FN, GPSR2_3,
2116 GP_2_2_FN, GPSR2_2,
2117 GP_2_1_FN, GPSR2_1,
2118 GP_2_0_FN, GPSR2_0, }
2119 },
2120 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2121 0, 0,
2122 0, 0,
2123 0, 0,
2124 0, 0,
2125 0, 0,
2126 0, 0,
2127 0, 0,
2128 0, 0,
2129 0, 0,
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 0, 0,
2140 0, 0,
2141 0, 0,
2142 0, 0,
2143 GP_3_9_FN, GPSR3_9,
2144 GP_3_8_FN, GPSR3_8,
2145 GP_3_7_FN, GPSR3_7,
2146 GP_3_6_FN, GPSR3_6,
2147 GP_3_5_FN, GPSR3_5,
2148 GP_3_4_FN, GPSR3_4,
2149 GP_3_3_FN, GPSR3_3,
2150 GP_3_2_FN, GPSR3_2,
2151 GP_3_1_FN, GPSR3_1,
2152 GP_3_0_FN, GPSR3_0, }
2153 },
2154 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2155 GP_4_31_FN, GPSR4_31,
2156 GP_4_30_FN, GPSR4_30,
2157 GP_4_29_FN, GPSR4_29,
2158 GP_4_28_FN, GPSR4_28,
2159 GP_4_27_FN, GPSR4_27,
2160 GP_4_26_FN, GPSR4_26,
2161 GP_4_25_FN, GPSR4_25,
2162 GP_4_24_FN, GPSR4_24,
2163 GP_4_23_FN, GPSR4_23,
2164 GP_4_22_FN, GPSR4_22,
2165 GP_4_21_FN, GPSR4_21,
2166 GP_4_20_FN, GPSR4_20,
2167 GP_4_19_FN, GPSR4_19,
2168 GP_4_18_FN, GPSR4_18,
2169 GP_4_17_FN, GPSR4_17,
2170 GP_4_16_FN, GPSR4_16,
2171 GP_4_15_FN, GPSR4_15,
2172 GP_4_14_FN, GPSR4_14,
2173 GP_4_13_FN, GPSR4_13,
2174 GP_4_12_FN, GPSR4_12,
2175 GP_4_11_FN, GPSR4_11,
2176 GP_4_10_FN, GPSR4_10,
2177 GP_4_9_FN, GPSR4_9,
2178 GP_4_8_FN, GPSR4_8,
2179 GP_4_7_FN, GPSR4_7,
2180 GP_4_6_FN, GPSR4_6,
2181 GP_4_5_FN, GPSR4_5,
2182 GP_4_4_FN, GPSR4_4,
2183 GP_4_3_FN, GPSR4_3,
2184 GP_4_2_FN, GPSR4_2,
2185 GP_4_1_FN, GPSR4_1,
2186 GP_4_0_FN, GPSR4_0, }
2187 },
2188 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2189 0, 0,
2190 0, 0,
2191 0, 0,
2192 0, 0,
2193 0, 0,
2194 0, 0,
2195 0, 0,
2196 0, 0,
2197 0, 0,
2198 0, 0,
2199 0, 0,
2200 GP_5_20_FN, GPSR5_20,
2201 GP_5_19_FN, GPSR5_19,
2202 GP_5_18_FN, GPSR5_18,
2203 GP_5_17_FN, GPSR5_17,
2204 GP_5_16_FN, GPSR5_16,
2205 GP_5_15_FN, GPSR5_15,
2206 GP_5_14_FN, GPSR5_14,
2207 GP_5_13_FN, GPSR5_13,
2208 GP_5_12_FN, GPSR5_12,
2209 GP_5_11_FN, GPSR5_11,
2210 GP_5_10_FN, GPSR5_10,
2211 GP_5_9_FN, GPSR5_9,
2212 GP_5_8_FN, GPSR5_8,
2213 GP_5_7_FN, GPSR5_7,
2214 GP_5_6_FN, GPSR5_6,
2215 GP_5_5_FN, GPSR5_5,
2216 GP_5_4_FN, GPSR5_4,
2217 GP_5_3_FN, GPSR5_3,
2218 GP_5_2_FN, GPSR5_2,
2219 GP_5_1_FN, GPSR5_1,
2220 GP_5_0_FN, GPSR5_0, }
2221 },
2222 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2223 0, 0,
2224 0, 0,
2225 0, 0,
2226 0, 0,
2227 0, 0,
2228 0, 0,
2229 0, 0,
2230 0, 0,
2231 0, 0,
2232 0, 0,
2233 0, 0,
2234 0, 0,
2235 0, 0,
2236 0, 0,
2237 0, 0,
2238 0, 0,
2239 0, 0,
2240 0, 0,
2241 GP_6_13_FN, GPSR6_13,
2242 GP_6_12_FN, GPSR6_12,
2243 GP_6_11_FN, GPSR6_11,
2244 GP_6_10_FN, GPSR6_10,
2245 GP_6_9_FN, GPSR6_9,
2246 GP_6_8_FN, GPSR6_8,
2247 GP_6_7_FN, GPSR6_7,
2248 GP_6_6_FN, GPSR6_6,
2249 GP_6_5_FN, GPSR6_5,
2250 GP_6_4_FN, GPSR6_4,
2251 GP_6_3_FN, GPSR6_3,
2252 GP_6_2_FN, GPSR6_2,
2253 GP_6_1_FN, GPSR6_1,
2254 GP_6_0_FN, GPSR6_0, }
2255 },
2256 #undef F_
2257 #undef FM
2258
2259 #define F_(x, y) x,
2260 #define FM(x) FN_##x,
2261 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2262 IP0_31_28
2263 IP0_27_24
2264 IP0_23_20
2265 IP0_19_16
2266 IP0_15_12
2267 IP0_11_8
2268 IP0_7_4
2269 IP0_3_0 }
2270 },
2271 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2272 IP1_31_28
2273 IP1_27_24
2274 IP1_23_20
2275 IP1_19_16
2276 IP1_15_12
2277 IP1_11_8
2278 IP1_7_4
2279 IP1_3_0 }
2280 },
2281 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2282 IP2_31_28
2283 IP2_27_24
2284 IP2_23_20
2285 IP2_19_16
2286 IP2_15_12
2287 IP2_11_8
2288 IP2_7_4
2289 IP2_3_0 }
2290 },
2291 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2292 IP3_31_28
2293 IP3_27_24
2294 IP3_23_20
2295 IP3_19_16
2296 IP3_15_12
2297 IP3_11_8
2298 IP3_7_4
2299 IP3_3_0 }
2300 },
2301 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2302 IP4_31_28
2303 IP4_27_24
2304 IP4_23_20
2305 IP4_19_16
2306 IP4_15_12
2307 IP4_11_8
2308 IP4_7_4
2309 IP4_3_0 }
2310 },
2311 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2312 IP5_31_28
2313 IP5_27_24
2314 IP5_23_20
2315 IP5_19_16
2316 IP5_15_12
2317 IP5_11_8
2318 IP5_7_4
2319 IP5_3_0 }
2320 },
2321 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2322 IP6_31_28
2323 IP6_27_24
2324 IP6_23_20
2325 IP6_19_16
2326 IP6_15_12
2327 IP6_11_8
2328 IP6_7_4
2329 IP6_3_0 }
2330 },
2331 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2332 IP7_31_28
2333 IP7_27_24
2334 IP7_23_20
2335 IP7_19_16
2336 IP7_15_12
2337 IP7_11_8
2338 IP7_7_4
2339 IP7_3_0 }
2340 },
2341 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2342 IP8_31_28
2343 IP8_27_24
2344 IP8_23_20
2345 IP8_19_16
2346 IP8_15_12
2347 IP8_11_8
2348 IP8_7_4
2349 IP8_3_0 }
2350 },
2351 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2352 IP9_31_28
2353 IP9_27_24
2354 IP9_23_20
2355 IP9_19_16
2356 IP9_15_12
2357 IP9_11_8
2358 IP9_7_4
2359 IP9_3_0 }
2360 },
2361 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2362 IP10_31_28
2363 IP10_27_24
2364 IP10_23_20
2365 IP10_19_16
2366 IP10_15_12
2367 IP10_11_8
2368 IP10_7_4
2369 IP10_3_0 }
2370 },
2371 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2372 IP11_31_28
2373 IP11_27_24
2374 IP11_23_20
2375 IP11_19_16
2376 IP11_15_12
2377 IP11_11_8
2378 IP11_7_4
2379 IP11_3_0 }
2380 },
2381 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2382 IP12_31_28
2383 IP12_27_24
2384 IP12_23_20
2385 IP12_19_16
2386 IP12_15_12
2387 IP12_11_8
2388 IP12_7_4
2389 IP12_3_0 }
2390 },
2391 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2392 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2393 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2394 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2395 /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2396 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2397 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2398 IP13_7_4
2399 IP13_3_0 }
2400 },
2401 #undef F_
2402 #undef FM
2403
2404 #define F_(x, y) x,
2405 #define FM(x) FN_##x,
2406 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2407 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
2408 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
2409 /* RESERVED 31 */
2410 0, 0,
2411 MOD_SEL0_30
2412 MOD_SEL0_29
2413 MOD_SEL0_28
2414 MOD_SEL0_27
2415 MOD_SEL0_26
2416 MOD_SEL0_25
2417 MOD_SEL0_24_23
2418 MOD_SEL0_22_21
2419 MOD_SEL0_20_19
2420 MOD_SEL0_18_17
2421 /* RESERVED 16 */
2422 0, 0,
2423 MOD_SEL0_15
2424 MOD_SEL0_14
2425 MOD_SEL0_13
2426 MOD_SEL0_12
2427 MOD_SEL0_11
2428 MOD_SEL0_10
2429 /* RESERVED 9, 8, 7, 6 */
2430 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2431 MOD_SEL0_5
2432 MOD_SEL0_4
2433 MOD_SEL0_3
2434 MOD_SEL0_2
2435 MOD_SEL0_1
2436 MOD_SEL0_0 }
2437 },
2438 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2439 1, 1, 1, 1, 1, 1, 2, 4, 4,
2440 4, 4, 4, 4) {
2441 MOD_SEL1_31
2442 MOD_SEL1_30
2443 MOD_SEL1_29
2444 MOD_SEL1_28
2445 MOD_SEL1_27
2446 MOD_SEL1_26
2447 /* RESERVED 25, 24 */
2448 0, 0, 0, 0,
2449 /* RESERVED 23, 22, 21, 20 */
2450 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2451 /* RESERVED 19, 18, 17, 16 */
2452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2453 /* RESERVED 15, 14, 13, 12 */
2454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2455 /* RESERVED 11, 10, 9, 8 */
2456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2457 /* RESERVED 7, 6, 5, 4 */
2458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2459 /* RESERVED 3, 2, 1, 0 */
2460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
2461 },
2462 { },
2463 };
2464
r8a77995_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)2465 static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2466 {
2467 int bit = -EINVAL;
2468
2469 *pocctrl = 0xe6060380;
2470
2471 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
2472 bit = 29 - (pin - RCAR_GP_PIN(3, 0));
2473
2474 return bit;
2475 }
2476
2477 static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
2478 .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
2479 };
2480
2481 const struct sh_pfc_soc_info r8a77995_pinmux_info = {
2482 .name = "r8a77995_pfc",
2483 .ops = &r8a77995_pinmux_ops,
2484 .unlock_reg = 0xe6060000, /* PMMR */
2485
2486 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2487
2488 .pins = pinmux_pins,
2489 .nr_pins = ARRAY_SIZE(pinmux_pins),
2490 .groups = pinmux_groups,
2491 .nr_groups = ARRAY_SIZE(pinmux_groups),
2492 .functions = pinmux_functions,
2493 .nr_functions = ARRAY_SIZE(pinmux_functions),
2494
2495 .cfg_regs = pinmux_config_regs,
2496
2497 .pinmux_data = pinmux_data,
2498 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2499 };
2500
