Searched refs:amdgpu_state (Results 1 – 3 of 3) sorted by relevance
2246 struct amdgpu_ps *amdgpu_state) in si_populate_smc_tdp_limits() argument2311 struct amdgpu_ps *amdgpu_state) in si_populate_smc_tdp_limits_2() argument2365 struct amdgpu_ps *amdgpu_state) in si_should_disable_uvd_powertune() argument2370 amdgpu_state->vclk && amdgpu_state->dclk) in si_should_disable_uvd_powertune()2384 struct amdgpu_ps *amdgpu_state, in si_populate_power_containment_values() argument2389 struct si_ps *state = si_get_ps(amdgpu_state); in si_populate_power_containment_values()2411 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state); in si_populate_power_containment_values()2477 struct amdgpu_ps *amdgpu_state, in si_populate_sq_ramping_values() argument2481 struct si_ps *state = si_get_ps(amdgpu_state); in si_populate_sq_ramping_values()4783 struct amdgpu_ps *amdgpu_state, in si_do_program_memory_timing_parameters() argument[all …]
3895 struct amdgpu_ps *amdgpu_state) in ci_trim_dpm_states() argument3897 struct ci_ps *state = ci_get_ps(amdgpu_state); in ci_trim_dpm_states()4003 struct amdgpu_ps *amdgpu_state) in ci_find_dpm_states_clocks_in_dpm_table() argument4006 struct ci_ps *state = ci_get_ps(amdgpu_state); in ci_find_dpm_states_clocks_in_dpm_table()4042 struct amdgpu_ps *amdgpu_state) in ci_populate_and_upload_sclk_mclk_dpm_levels() argument4045 struct ci_ps *state = ci_get_ps(amdgpu_state); in ci_populate_and_upload_sclk_mclk_dpm_levels()4316 struct amdgpu_ps *amdgpu_state) in ci_generate_dpm_level_enable_mask() argument4321 ret = ci_trim_dpm_states(adev, amdgpu_state); in ci_generate_dpm_level_enable_mask()4947 struct amdgpu_ps *amdgpu_state) in ci_get_maximum_link_speed() argument4949 struct ci_ps *state = ci_get_ps(amdgpu_state); in ci_get_maximum_link_speed()
3121 struct dm_plane_state *amdgpu_state = NULL; in dm_drm_plane_reset() local3126 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); in dm_drm_plane_reset()3127 WARN_ON(amdgpu_state == NULL); in dm_drm_plane_reset()3129 if (amdgpu_state) { in dm_drm_plane_reset()3130 plane->state = &amdgpu_state->base; in dm_drm_plane_reset()
