Home
last modified time | relevance | path

Searched refs:amdgpu_ring_write (Results 1 – 21 of 21) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c922 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
924 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
925 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
927 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
941 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
943 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
961 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
963 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
964 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
966 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v1_0_dec_ring_emit_fence()
[all …]
Duvd_v6_0.c183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v6_0_enc_ring_test_ring()
497 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
498 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
501 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
502 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
505 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
506 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
509 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
510 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
512 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
[all …]
Duvd_v5_0.c175 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
176 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
179 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
180 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
183 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
184 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
187 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
188 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
191 amdgpu_ring_write(ring, 3); in uvd_v5_0_hw_init()
[all …]
Duvd_v4_2.c179 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
180 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
183 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
184 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
187 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
188 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
191 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
192 amdgpu_ring_write(ring, 0x8); in uvd_v4_2_hw_init()
194 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
195 amdgpu_ring_write(ring, 3); in uvd_v4_2_hw_init()
[all …]
Dsi_dma.c71 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_dma_ring_emit_ib()
72 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); in si_dma_ring_emit_ib()
73 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
74 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
94 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
95 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
96 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
97 amdgpu_ring_write(ring, seq); in si_dma_ring_emit_fence()
101 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
102 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
[all …]
Duvd_v7_0.c191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
555 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
556 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
560 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
561 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
565 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
566 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
569 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
571 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
[all …]
Dsdma_v2_4.c233 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v2_4_ring_insert_nop()
236 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v2_4_ring_insert_nop()
254 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
257 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
258 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
259 amdgpu_ring_write(ring, ib->length_dw); in sdma_v2_4_ring_emit_ib()
260 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
261 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
281 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v2_4_ring_emit_hdp_flush()
284 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v2_4_ring_emit_hdp_flush()
[all …]
Dcik_sdma.c206 amdgpu_ring_write(ring, ring->funcs->nop | in cik_sdma_ring_insert_nop()
209 amdgpu_ring_write(ring, ring->funcs->nop); in cik_sdma_ring_insert_nop()
229 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_emit_ib()
230 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
231 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
232 amdgpu_ring_write(ring, ib->length_dw); in cik_sdma_ring_emit_ib()
254 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_ring_emit_hdp_flush()
255 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in cik_sdma_ring_emit_hdp_flush()
256 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in cik_sdma_ring_emit_hdp_flush()
257 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
[all …]
Dsdma_v3_0.c408 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v3_0_ring_insert_nop()
411 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v3_0_ring_insert_nop()
429 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
432 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
433 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
434 amdgpu_ring_write(ring, ib->length_dw); in sdma_v3_0_ring_emit_ib()
435 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
436 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
456 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v3_0_ring_emit_hdp_flush()
459 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v3_0_ring_emit_hdp_flush()
[all …]
Dgfx_v7_0.c2078 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2079 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v7_0_ring_test_ring()
2080 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2128 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2129 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2132 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2133 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2134 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2135 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2136 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
[all …]
Dgfx_v9_0.c307 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
308 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | in gfx_v9_0_write_data_to_reg()
311 amdgpu_ring_write(ring, reg); in gfx_v9_0_write_data_to_reg()
312 amdgpu_ring_write(ring, 0); in gfx_v9_0_write_data_to_reg()
313 amdgpu_ring_write(ring, val); in gfx_v9_0_write_data_to_reg()
321 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
322 amdgpu_ring_write(ring, in gfx_v9_0_wait_reg_mem()
331 amdgpu_ring_write(ring, addr0); in gfx_v9_0_wait_reg_mem()
332 amdgpu_ring_write(ring, addr1); in gfx_v9_0_wait_reg_mem()
333 amdgpu_ring_write(ring, ref); in gfx_v9_0_wait_reg_mem()
[all …]
Dgfx_v6_0.c1790 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1791 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_test_ring()
1792 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1814 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1815 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | in gfx_v6_0_ring_emit_vgt_flush()
1825 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1826 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_emit_fence()
1827 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1828 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1829 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in gfx_v6_0_ring_emit_fence()
[all …]
Dgfx_v8_0.c854 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
855 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v8_0_ring_test_ring()
856 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
4394 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4395 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
4397 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4398 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4399 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4404 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
4407 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
[all …]
Dsdma_v4_0.c366 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_0_ring_insert_nop()
369 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_0_ring_insert_nop()
387 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_0_ring_emit_ib()
390 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
391 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_0_ring_emit_ib()
392 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_0_ring_emit_ib()
393 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
394 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
404 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_0_wait_reg_mem()
410 amdgpu_ring_write(ring, addr0); in sdma_v4_0_wait_reg_mem()
[all …]
Dvce_v3_0.c843 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v3_0_ring_emit_ib()
844 amdgpu_ring_write(ring, vmid); in vce_v3_0_ring_emit_ib()
845 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
846 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
847 amdgpu_ring_write(ring, ib->length_dw); in vce_v3_0_ring_emit_ib()
853 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB); in vce_v3_0_emit_vm_flush()
854 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
855 amdgpu_ring_write(ring, pd_addr >> 12); in vce_v3_0_emit_vm_flush()
857 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB); in vce_v3_0_emit_vm_flush()
858 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
[all …]
Dvce_v4_0.c952 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v4_0_ring_emit_ib()
953 amdgpu_ring_write(ring, vmid); in vce_v4_0_ring_emit_ib()
954 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
955 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
956 amdgpu_ring_write(ring, ib->length_dw); in vce_v4_0_ring_emit_ib()
964 amdgpu_ring_write(ring, VCE_CMD_FENCE); in vce_v4_0_ring_emit_fence()
965 amdgpu_ring_write(ring, addr); in vce_v4_0_ring_emit_fence()
966 amdgpu_ring_write(ring, upper_32_bits(addr)); in vce_v4_0_ring_emit_fence()
967 amdgpu_ring_write(ring, seq); in vce_v4_0_ring_emit_fence()
968 amdgpu_ring_write(ring, VCE_CMD_TRAP); in vce_v4_0_ring_emit_fence()
[all …]
Damdgpu_vce.c1038 amdgpu_ring_write(ring, VCE_CMD_IB); in amdgpu_vce_ring_emit_ib()
1039 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1040 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1041 amdgpu_ring_write(ring, ib->length_dw); in amdgpu_vce_ring_emit_ib()
1056 amdgpu_ring_write(ring, VCE_CMD_FENCE); in amdgpu_vce_ring_emit_fence()
1057 amdgpu_ring_write(ring, addr); in amdgpu_vce_ring_emit_fence()
1058 amdgpu_ring_write(ring, upper_32_bits(addr)); in amdgpu_vce_ring_emit_fence()
1059 amdgpu_ring_write(ring, seq); in amdgpu_vce_ring_emit_fence()
1060 amdgpu_ring_write(ring, VCE_CMD_TRAP); in amdgpu_vce_ring_emit_fence()
1061 amdgpu_ring_write(ring, VCE_CMD_END); in amdgpu_vce_ring_emit_fence()
[all …]
Damdgpu_vcn.c263 amdgpu_ring_write(ring, in amdgpu_vcn_dec_ring_test_ring()
265 amdgpu_ring_write(ring, 0xDEADBEEF); in amdgpu_vcn_dec_ring_test_ring()
444 amdgpu_ring_write(ring, VCN_ENC_CMD_END); in amdgpu_vcn_enc_ring_test_ring()
617 amdgpu_ring_write(ring, in amdgpu_vcn_jpeg_ring_test_ring()
619 amdgpu_ring_write(ring, 0xDEADBEEF); in amdgpu_vcn_jpeg_ring_test_ring()
Damdgpu_ring.h253 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) in amdgpu_ring_write() function
Damdgpu_ring.c97 amdgpu_ring_write(ring, ring->funcs->nop); in amdgpu_ring_insert_nop()
Damdgpu_amdkfd_gfx_v9.c849 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in invalidate_tlbs_with_kiq()
850 amdgpu_ring_write(ring, in invalidate_tlbs_with_kiq()