1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Adjunct processor (AP) interfaces
4 *
5 * Copyright IBM Corp. 2017
6 *
7 * Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com>
8 * Martin Schwidefsky <schwidefsky@de.ibm.com>
9 * Harald Freudenberger <freude@de.ibm.com>
10 */
11
12 #ifndef _ASM_S390_AP_H_
13 #define _ASM_S390_AP_H_
14
15 /**
16 * The ap_qid_t identifier of an ap queue.
17 * If the AP facilities test (APFT) facility is available,
18 * card and queue index are 8 bit values, otherwise
19 * card index is 6 bit and queue index a 4 bit value.
20 */
21 typedef unsigned int ap_qid_t;
22
23 #define AP_MKQID(_card, _queue) (((_card) & 0xff) << 8 | ((_queue) & 0xff))
24 #define AP_QID_CARD(_qid) (((_qid) >> 8) & 0xff)
25 #define AP_QID_QUEUE(_qid) ((_qid) & 0xff)
26
27 /**
28 * struct ap_queue_status - Holds the AP queue status.
29 * @queue_empty: Shows if queue is empty
30 * @replies_waiting: Waiting replies
31 * @queue_full: Is 1 if the queue is full
32 * @irq_enabled: Shows if interrupts are enabled for the AP
33 * @response_code: Holds the 8 bit response code
34 *
35 * The ap queue status word is returned by all three AP functions
36 * (PQAP, NQAP and DQAP). There's a set of flags in the first
37 * byte, followed by a 1 byte response code.
38 */
39 struct ap_queue_status {
40 unsigned int queue_empty : 1;
41 unsigned int replies_waiting : 1;
42 unsigned int queue_full : 1;
43 unsigned int _pad1 : 4;
44 unsigned int irq_enabled : 1;
45 unsigned int response_code : 8;
46 unsigned int _pad2 : 16;
47 };
48
49 /**
50 * ap_intructions_available() - Test if AP instructions are available.
51 *
52 * Returns true if the AP instructions are installed, otherwise false.
53 */
ap_instructions_available(void)54 static inline bool ap_instructions_available(void)
55 {
56 register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
57 register unsigned long reg1 asm ("1") = 0;
58 register unsigned long reg2 asm ("2") = 0;
59
60 asm volatile(
61 " .long 0xb2af0000\n" /* PQAP(TAPQ) */
62 "0: la %0,1\n"
63 "1:\n"
64 EX_TABLE(0b, 1b)
65 : "+d" (reg1), "+d" (reg2)
66 : "d" (reg0)
67 : "cc");
68 return reg1 != 0;
69 }
70
71 /**
72 * ap_tapq(): Test adjunct processor queue.
73 * @qid: The AP queue number
74 * @info: Pointer to queue descriptor
75 *
76 * Returns AP queue status structure.
77 */
ap_tapq(ap_qid_t qid,unsigned long * info)78 static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
79 {
80 register unsigned long reg0 asm ("0") = qid;
81 register struct ap_queue_status reg1 asm ("1");
82 register unsigned long reg2 asm ("2");
83
84 asm volatile(".long 0xb2af0000" /* PQAP(TAPQ) */
85 : "=d" (reg1), "=d" (reg2)
86 : "d" (reg0)
87 : "cc");
88 if (info)
89 *info = reg2;
90 return reg1;
91 }
92
93 /**
94 * ap_test_queue(): Test adjunct processor queue.
95 * @qid: The AP queue number
96 * @tbit: Test facilities bit
97 * @info: Pointer to queue descriptor
98 *
99 * Returns AP queue status structure.
100 */
ap_test_queue(ap_qid_t qid,int tbit,unsigned long * info)101 static inline struct ap_queue_status ap_test_queue(ap_qid_t qid,
102 int tbit,
103 unsigned long *info)
104 {
105 if (tbit)
106 qid |= 1UL << 23; /* set T bit*/
107 return ap_tapq(qid, info);
108 }
109
110 /**
111 * ap_pqap_rapq(): Reset adjunct processor queue.
112 * @qid: The AP queue number
113 *
114 * Returns AP queue status structure.
115 */
ap_rapq(ap_qid_t qid)116 static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
117 {
118 register unsigned long reg0 asm ("0") = qid | (1UL << 24);
119 register struct ap_queue_status reg1 asm ("1");
120
121 asm volatile(
122 ".long 0xb2af0000" /* PQAP(RAPQ) */
123 : "=d" (reg1)
124 : "d" (reg0)
125 : "cc");
126 return reg1;
127 }
128
129 /**
130 * ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
131 * @qid: The AP queue number
132 *
133 * Returns AP queue status structure.
134 */
ap_zapq(ap_qid_t qid)135 static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
136 {
137 register unsigned long reg0 asm ("0") = qid | (2UL << 24);
138 register struct ap_queue_status reg1 asm ("1");
139
140 asm volatile(
141 ".long 0xb2af0000" /* PQAP(ZAPQ) */
142 : "=d" (reg1)
143 : "d" (reg0)
144 : "cc");
145 return reg1;
146 }
147
148 /**
149 * struct ap_config_info - convenience struct for AP crypto
150 * config info as returned by the ap_qci() function.
151 */
152 struct ap_config_info {
153 unsigned int apsc : 1; /* S bit */
154 unsigned int apxa : 1; /* N bit */
155 unsigned int qact : 1; /* C bit */
156 unsigned int rc8a : 1; /* R bit */
157 unsigned char _reserved1 : 4;
158 unsigned char _reserved2[3];
159 unsigned char Na; /* max # of APs - 1 */
160 unsigned char Nd; /* max # of Domains - 1 */
161 unsigned char _reserved3[10];
162 unsigned int apm[8]; /* AP ID mask */
163 unsigned int aqm[8]; /* AP queue mask */
164 unsigned int adm[8]; /* AP domain mask */
165 unsigned char _reserved4[16];
166 } __aligned(8);
167
168 /**
169 * ap_qci(): Get AP configuration data
170 *
171 * Returns 0 on success, or -EOPNOTSUPP.
172 */
ap_qci(struct ap_config_info * config)173 static inline int ap_qci(struct ap_config_info *config)
174 {
175 register unsigned long reg0 asm ("0") = 4UL << 24;
176 register unsigned long reg1 asm ("1") = -EOPNOTSUPP;
177 register struct ap_config_info *reg2 asm ("2") = config;
178
179 asm volatile(
180 ".long 0xb2af0000\n" /* PQAP(QCI) */
181 "0: la %0,0\n"
182 "1:\n"
183 EX_TABLE(0b, 1b)
184 : "+d" (reg1)
185 : "d" (reg0), "d" (reg2)
186 : "cc", "memory");
187
188 return reg1;
189 }
190
191 /*
192 * struct ap_qirq_ctrl - convenient struct for easy invocation
193 * of the ap_aqic() function. This struct is passed as GR1
194 * parameter to the PQAP(AQIC) instruction. For details please
195 * see the AR documentation.
196 */
197 struct ap_qirq_ctrl {
198 unsigned int _res1 : 8;
199 unsigned int zone : 8; /* zone info */
200 unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */
201 unsigned int _res2 : 4;
202 unsigned int gisc : 3; /* guest isc field */
203 unsigned int _res3 : 6;
204 unsigned int gf : 2; /* gisa format */
205 unsigned int _res4 : 1;
206 unsigned int gisa : 27; /* gisa origin */
207 unsigned int _res5 : 1;
208 unsigned int isc : 3; /* irq sub class */
209 };
210
211 /**
212 * ap_aqic(): Control interruption for a specific AP.
213 * @qid: The AP queue number
214 * @qirqctrl: struct ap_qirq_ctrl (64 bit value)
215 * @ind: The notification indicator byte
216 *
217 * Returns AP queue status.
218 */
ap_aqic(ap_qid_t qid,struct ap_qirq_ctrl qirqctrl,void * ind)219 static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
220 struct ap_qirq_ctrl qirqctrl,
221 void *ind)
222 {
223 register unsigned long reg0 asm ("0") = qid | (3UL << 24);
224 register struct ap_qirq_ctrl reg1_in asm ("1") = qirqctrl;
225 register struct ap_queue_status reg1_out asm ("1");
226 register void *reg2 asm ("2") = ind;
227
228 asm volatile(
229 ".long 0xb2af0000" /* PQAP(AQIC) */
230 : "=d" (reg1_out)
231 : "d" (reg0), "d" (reg1_in), "d" (reg2)
232 : "cc");
233 return reg1_out;
234 }
235
236 /*
237 * union ap_qact_ap_info - used together with the
238 * ap_aqic() function to provide a convenient way
239 * to handle the ap info needed by the qact function.
240 */
241 union ap_qact_ap_info {
242 unsigned long val;
243 struct {
244 unsigned int : 3;
245 unsigned int mode : 3;
246 unsigned int : 26;
247 unsigned int cat : 8;
248 unsigned int : 8;
249 unsigned char ver[2];
250 };
251 };
252
253 /**
254 * ap_qact(): Query AP combatibility type.
255 * @qid: The AP queue number
256 * @apinfo: On input the info about the AP queue. On output the
257 * alternate AP queue info provided by the qact function
258 * in GR2 is stored in.
259 *
260 * Returns AP queue status. Check response_code field for failures.
261 */
ap_qact(ap_qid_t qid,int ifbit,union ap_qact_ap_info * apinfo)262 static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
263 union ap_qact_ap_info *apinfo)
264 {
265 register unsigned long reg0 asm ("0") = qid | (5UL << 24)
266 | ((ifbit & 0x01) << 22);
267 register unsigned long reg1_in asm ("1") = apinfo->val;
268 register struct ap_queue_status reg1_out asm ("1");
269 register unsigned long reg2 asm ("2");
270
271 asm volatile(
272 ".long 0xb2af0000" /* PQAP(QACT) */
273 : "+d" (reg1_in), "=d" (reg1_out), "=d" (reg2)
274 : "d" (reg0)
275 : "cc");
276 apinfo->val = reg2;
277 return reg1_out;
278 }
279
280 /**
281 * ap_nqap(): Send message to adjunct processor queue.
282 * @qid: The AP queue number
283 * @psmid: The program supplied message identifier
284 * @msg: The message text
285 * @length: The message length
286 *
287 * Returns AP queue status structure.
288 * Condition code 1 on NQAP can't happen because the L bit is 1.
289 * Condition code 2 on NQAP also means the send is incomplete,
290 * because a segment boundary was reached. The NQAP is repeated.
291 */
ap_nqap(ap_qid_t qid,unsigned long long psmid,void * msg,size_t length)292 static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
293 unsigned long long psmid,
294 void *msg, size_t length)
295 {
296 register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
297 register struct ap_queue_status reg1 asm ("1");
298 register unsigned long reg2 asm ("2") = (unsigned long) msg;
299 register unsigned long reg3 asm ("3") = (unsigned long) length;
300 register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
301 register unsigned long reg5 asm ("5") = psmid & 0xffffffff;
302
303 asm volatile (
304 "0: .long 0xb2ad0042\n" /* NQAP */
305 " brc 2,0b"
306 : "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
307 : "d" (reg4), "d" (reg5)
308 : "cc", "memory");
309 return reg1;
310 }
311
312 /**
313 * ap_dqap(): Receive message from adjunct processor queue.
314 * @qid: The AP queue number
315 * @psmid: Pointer to program supplied message identifier
316 * @msg: The message text
317 * @length: The message length
318 *
319 * Returns AP queue status structure.
320 * Condition code 1 on DQAP means the receive has taken place
321 * but only partially. The response is incomplete, hence the
322 * DQAP is repeated.
323 * Condition code 2 on DQAP also means the receive is incomplete,
324 * this time because a segment boundary was reached. Again, the
325 * DQAP is repeated.
326 * Note that gpr2 is used by the DQAP instruction to keep track of
327 * any 'residual' length, in case the instruction gets interrupted.
328 * Hence it gets zeroed before the instruction.
329 */
ap_dqap(ap_qid_t qid,unsigned long long * psmid,void * msg,size_t length)330 static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
331 unsigned long long *psmid,
332 void *msg, size_t length)
333 {
334 register unsigned long reg0 asm("0") = qid | 0x80000000UL;
335 register struct ap_queue_status reg1 asm ("1");
336 register unsigned long reg2 asm("2") = 0UL;
337 register unsigned long reg4 asm("4") = (unsigned long) msg;
338 register unsigned long reg5 asm("5") = (unsigned long) length;
339 register unsigned long reg6 asm("6") = 0UL;
340 register unsigned long reg7 asm("7") = 0UL;
341
342
343 asm volatile(
344 "0: .long 0xb2ae0064\n" /* DQAP */
345 " brc 6,0b\n"
346 : "+d" (reg0), "=d" (reg1), "+d" (reg2),
347 "+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
348 : : "cc", "memory");
349 *psmid = (((unsigned long long) reg6) << 32) + reg7;
350 return reg1;
351 }
352
353 #endif /* _ASM_S390_AP_H_ */
354
