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Searched refs:_reg (Results 1 – 25 of 99) sorted by relevance

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/Linux-v4.19/drivers/net/ethernet/amd/xgbe/
Dxgbe-common.h1442 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1443 ioread32((_pdata)->xgmac_regs + _reg)
1445 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument
1446 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1447 _reg##_##_field##_INDEX, \
1448 _reg##_##_field##_WIDTH)
1450 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1451 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1453 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument
1455 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
[all …]
/Linux-v4.19/drivers/regulator/
Dmc13xxx.h59 #define MC13xxx_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages, _ops) \ argument
70 .reg = prefix ## _reg, \
71 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
77 #define MC13xxx_FIXED_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
88 .reg = prefix ## _reg, \
89 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
92 #define MC13xxx_GPO_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
103 .reg = prefix ## _reg, \
104 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
107 #define MC13xxx_DEFINE_SW(_name, _reg, _vsel_reg, _voltages, ops) \ argument
[all …]
/Linux-v4.19/drivers/clk/zte/
Dclk.h40 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
42 .reg_base = (void __iomem *) _reg, \
55 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
56 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
63 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
66 .reg = (void __iomem *) _reg, \
101 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
104 .reg = (void __iomem *) _reg, \
117 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
118 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
[all …]
/Linux-v4.19/drivers/clk/sunxi-ng/
Dccu_div.h95 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
103 .reg = _reg, \
112 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
115 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
121 _reg, \ argument
130 .reg = _reg, \
138 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
143 _reg, _mshift, _mwidth, \
147 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
152 _reg, _mshift, _mwidth, \
[all …]
Dccu_mp.h42 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
54 .reg = _reg, \
63 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
74 .reg = _reg, \
82 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
87 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
111 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
119 .reg = _reg, \
Dccu_nm.h45 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
59 .reg = _reg, \
68 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
83 .reg = _reg, \
93 _reg, _min_rate, \ argument
109 .reg = _reg, \
118 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
128 .reg = _reg, \
Dccu_mux.h51 _reg, _shift, _width, _gate, \ argument
57 .reg = _reg, \
65 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
68 _reg, _shift, _width, _gate, \
71 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
74 _reg, _shift, _width, 0, _flags)
/Linux-v4.19/drivers/clk/pistachio/
Dclk.h22 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
25 .reg = _reg, \
42 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
45 .reg = _reg, \
62 #define DIV(_id, _name, _pname, _reg, _width) \ argument
65 .reg = _reg, \
72 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
75 .reg = _reg, \
122 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
125 .reg_base = _reg, \
[all …]
/Linux-v4.19/arch/arm/mach-mmp/
Dclock.h29 #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ argument
31 .clk_rst = APBC_##_reg, \
37 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ argument
39 .clk_rst = APBC_##_reg, \
45 #define APMU_CLK(_name, _reg, _eval, _rate) \ argument
47 .clk_rst = APMU_##_reg, \
53 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ argument
55 .clk_rst = APMU_##_reg, \
/Linux-v4.19/arch/mips/include/asm/mach-pic32/
Dpic32.h22 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument
23 #define PIC32_SET(_reg) ((_reg) + 0x08) argument
24 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
/Linux-v4.19/drivers/clk/meson/
Daxg-audio.c24 #define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags) \ argument
27 .offset = (_reg), \
39 #define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \ argument
42 .offset = (_reg), \
56 #define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \ argument
59 .offset = (_reg), \
104 #define AXG_MST_MCLK_MUX(_name, _reg) \ argument
105 AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, CLK_MUX_ROUND_CLOSEST, \
119 #define AXG_MST_MCLK_DIV(_name, _reg) \ argument
120 AXG_AUD_DIV(_name##_div, _reg, 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \
[all …]
/Linux-v4.19/drivers/clk/sprd/
Dgate.h21 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
29 .reg = _reg, \
37 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
39 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
43 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
45 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
Dpll.h64 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
78 .reg = _reg, \
86 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
89 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
93 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
Dcomposite.h21 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
28 .reg = _reg, \
36 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
38 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \
/Linux-v4.19/drivers/clk/actions/
Dowl-gate.h27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
29 .reg = _reg, \
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
37 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
50 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
Dowl-pll.h38 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
41 .reg = _reg, \
51 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
54 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
66 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
69 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
29 .reg = _reg, \
34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
31 .reg = _reg, \
38 #define OWL_DIVIDER(_struct, _name, _parent, _reg, \ argument
41 .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
/Linux-v4.19/drivers/clk/mediatek/
Dclk-mtk.h91 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
95 .mux_reg = _reg, \
98 .gate_reg = _reg, \
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
111 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
114 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ argument
117 .mux_reg = _reg, \
180 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
184 .div_reg = _reg, \
/Linux-v4.19/drivers/media/tuners/
Dmc44s803_priv.h189 #define MC44S803_REG_SM(_val, _reg) \ argument
190 (((_val) << _reg##_S) & (_reg))
193 #define MC44S803_REG_MS(_val, _reg) \ argument
194 (((_val) & (_reg)) >> _reg##_S)
/Linux-v4.19/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.h33 #define A6XX_PROTECT_RW(_reg, _len) \ argument
35 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
42 #define A6XX_PROTECT_RDONLY(_reg, _len) \ argument
43 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
Dadreno_gpu.h30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 argument
275 #define PKT4(_reg, _cnt) \ argument
277 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
365 #define ADRENO_PROTECT_RW(_reg, _len) \ argument
367 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
374 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ argument
376 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
/Linux-v4.19/arch/mips/include/asm/
Dkvm_host.h468 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ argument
471 return cop0->reg[(_reg)][(sel)]; \
476 cop0->reg[(_reg)][(sel)] = val; \
480 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ argument
484 cop0->reg[(_reg)][(sel)] |= val; \
489 cop0->reg[(_reg)][(sel)] &= ~val; \
496 cop0->reg[(_reg)][(sel)] &= ~_mask; \
497 cop0->reg[(_reg)][(sel)] |= val & _mask; \
501 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ argument
505 _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
[all …]
/Linux-v4.19/include/linux/
Dsh_clk.h151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
154 .enable_reg = (void __iomem *)_reg, \
175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
178 .enable_reg = (void __iomem *)_reg, \
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
191 .enable_reg = (void __iomem *)_reg, \
205 #define SH_CLK_FSIDIV(_reg, _parent) \ argument
207 .enable_reg = (void __iomem *)_reg, \
/Linux-v4.19/drivers/reset/sti/
Dreset-stih407.c61 #define STIH407_SRST_CORE(_reg, _bit) \ argument
62 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
64 #define STIH407_SRST_SBC(_reg, _bit) \ argument
65 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
67 #define STIH407_SRST_LPM(_reg, _bit) \ argument
68 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)

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