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Searched refs:_MMIO (Results 1 – 25 of 26) sorted by relevance

12

/Linux-v4.19/drivers/gpu/drm/i915/
Di915_oa_hsw.c35 { _MMIO(0x2724), 0x00800000 },
36 { _MMIO(0x2720), 0x00000000 },
37 { _MMIO(0x2714), 0x00800000 },
38 { _MMIO(0x2710), 0x00000000 },
45 { _MMIO(0x9840), 0x00000080 },
46 { _MMIO(0x253a4), 0x01600000 },
47 { _MMIO(0x25440), 0x00100000 },
48 { _MMIO(0x25128), 0x00000000 },
49 { _MMIO(0x2691c), 0x00000800 },
50 { _MMIO(0x26aa0), 0x01500000 },
[all …]
Di915_oa_cnl.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2710), 0x00000000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2720), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2770), 0x00000004 },
41 { _MMIO(0x2774), 0x0000ffff },
42 { _MMIO(0x2778), 0x00000003 },
43 { _MMIO(0x277c), 0x0000ffff },
44 { _MMIO(0x2780), 0x00000007 },
[all …]
Di915_oa_icl.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2710), 0x00000000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2720), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2770), 0x00000004 },
41 { _MMIO(0x2774), 0x0000ffff },
42 { _MMIO(0x2778), 0x00000003 },
43 { _MMIO(0x277c), 0x0000ffff },
44 { _MMIO(0x2780), 0x00000007 },
[all …]
Di915_oa_bdw.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_chv.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_kblgt2.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_kblgt3.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_cflgt2.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_cflgt3.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_sklgt3.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_sklgt4.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_bxt.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_glk.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2744), 0x00800000 },
37 { _MMIO(0x2714), 0xf0800000 },
38 { _MMIO(0x2710), 0x00000000 },
39 { _MMIO(0x2724), 0xf0800000 },
40 { _MMIO(0x2720), 0x00000000 },
41 { _MMIO(0x2770), 0x00000004 },
42 { _MMIO(0x2774), 0x00000000 },
43 { _MMIO(0x2778), 0x00000003 },
44 { _MMIO(0x277c), 0x00000000 },
[all …]
Di915_oa_sklgt2.c35 { _MMIO(0x2740), 0x00000000 },
36 { _MMIO(0x2714), 0xf0800000 },
37 { _MMIO(0x2710), 0x00000000 },
38 { _MMIO(0x2724), 0xf0800000 },
39 { _MMIO(0x2720), 0x00000000 },
40 { _MMIO(0x2770), 0x00000004 },
41 { _MMIO(0x2774), 0x00000000 },
42 { _MMIO(0x2778), 0x00000003 },
43 { _MMIO(0x277c), 0x00000000 },
44 { _MMIO(0x2780), 0x00000007 },
[all …]
Dintel_guc_reg.h29 #define GUC_STATUS _MMIO(0xc000)
51 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
54 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
57 #define DMA_ADDR_0_LOW _MMIO(0xc300)
58 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
59 #define DMA_ADDR_1_LOW _MMIO(0xc308)
60 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
63 #define DMA_COPY_SIZE _MMIO(0xc310)
64 #define DMA_CTRL _MMIO(0xc314)
68 #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
[all …]
Di915_reg.h123 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) macro
125 #define INVALID_MMIO_REG _MMIO(0)
161 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
165 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
167 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
168 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
169 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
171 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
173 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
289 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
[all …]
Dintel_lrc.h33 #define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
34 #define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
35 #define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
36 #define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
41 #define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
42 #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
43 #define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
44 #define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
45 #define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510)
46 #define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550)
Di915_pvinfo.h114 _MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)))
Dintel_csr.c388 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); in parse_csr_fw()
Dintel_guc.c45 return _MMIO(guc->send_regs.base + 4 * i); in guc_send_reg()
Dintel_i2c.c295 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + in intel_gpio_setup()
/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dhandlers.c44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
464 _MMIO(0x2690),
465 _MMIO(0x2694),
466 _MMIO(0x2698),
467 _MMIO(0x4de0),
468 _MMIO(0x4de4),
[all …]
Dmmio_context.c44 #define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i)*4)
45 #define TRNULLDETCT _MMIO(0x4de8)
46 #define TRINVTILEDETCT _MMIO(0x4dec)
47 #define TRVADR _MMIO(0x4df0)
48 #define TRTTE _MMIO(0x4df4)
49 #define RING_EXCC(base) _MMIO((base) + 0x28)
50 #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
51 #define VF_GUARDBAND _MMIO(0x83a4)
358 reg = _MMIO(regs[ring_id]); in handle_tlb_pending_event()
Ddebugfs.c66 preg = I915_READ_NOTRACE(_MMIO(offset)); in mmio_diff_handler()
Dfirmware.c73 *(u32 *)(data + offset) = I915_READ_NOTRACE(_MMIO(offset)); in mmio_snapshot_handler()

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