Home
last modified time | relevance | path

Searched refs:_MASKED_BIT_ENABLE (Results 1 – 15 of 15) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_workarounds.c105 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
595 _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); in gen9_gt_workarounds_apply()
637 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); in gen9_gt_workarounds_apply()
665 _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE)); in bxt_gt_workarounds_apply()
814 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); in cnl_gt_workarounds_apply()
823 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE)); in icl_gt_workarounds_apply()
Dintel_ringbuffer.c414 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in intel_ring_setup_status_page()
429 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); in stop_ring()
626 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()
635 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in init_render_ring()
641 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); in init_render_ring()
646 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | in init_render_ring()
647 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); in init_render_ring()
660 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
1573 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
1924 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); in gen6_bsd_submit_request()
Dintel_huc_fw.c136 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA)); in huc_fw_xfer()
Dintel_pm.c374 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
385 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : in _intel_set_memory_cxsr()
7537 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in cherryview_enable_rc6()
7626 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in valleyview_enable_rc6()
8477 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); in ilk_init_clock_gating()
8545 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); in gen6_init_clock_gating()
8588 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); in gen6_init_clock_gating()
8596 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); in gen6_init_clock_gating()
8722 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE)); in cnl_init_clock_gating()
8822 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in bdw_init_clock_gating()
[all …]
Dintel_lrc.c545 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | in inject_preempt_context()
547 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | in inject_preempt_context()
1753 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); in enable_execlists()
1814 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in gen8_init_render_ring()
1816 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in gen8_init_render_ring()
2589 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | in execlists_init_reg_state()
2709 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in populate_lr_context()
2712 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | in populate_lr_context()
Dintel_guc_fw.c180 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); in guc_xfer_ucode()
Dintel_guc_submission.c1034 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | \ in ctx_save_restore_disabled()
1202 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); in guc_interrupts_capture()
Dintel_uncore.c152 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL_FALLBACK)); in fw_domain_wait_ack_with_fallback()
1398 dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); in intel_uncore_fw_domains_init()
2075 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); in gen8_reset_engine_start()
Di915_perf.c1902 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen8_enable_metric_set()
3128 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); in mask_reg_value()
3135 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); in mask_reg_value()
Di915_gem_gtt.c1805 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); in gen8_ppgtt_enable()
1830 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen7_ppgtt_enable()
1848 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
Dintel_engine_cs.c786 I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING)); in intel_engine_stop_cs()
Di915_gem.c5204 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
5206 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
5208 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in i915_gem_init_swizzling()
Di915_reg.h185 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro
/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dmmio_context.c454 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in is_inhibit_context()
Dhandlers.c1687 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || in ring_mode_mmio_write()
1688 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) in ring_mode_mmio_write()
1693 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) in ring_mode_mmio_write()
1755 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) in ring_reset_ctl_write()
2691 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, in init_broadwell_mmio_info()