Searched refs:_AC (Results 1 – 25 of 61) sorted by relevance
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18 #define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */19 #define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable */20 #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */21 #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/22 #define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */23 #define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */24 #define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */25 #define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */26 #define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/27 #define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */[all …]
8 #define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */9 #define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */10 #define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */11 #define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */12 #define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */13 #define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */14 #define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */15 #define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/16 #define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */17 #define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */[all …]
9 #define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)11 #define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)13 #define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)15 #define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)17 #define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)19 #define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)21 #define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)23 #define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)25 #define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)27 #define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)[all …]
8 #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/9 #define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/10 #define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/11 #define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/12 #define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/13 #define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/14 #define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */15 #define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */16 #define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */17 #define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */[all …]
37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)38 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL)39 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL)40 #define MODULES_VADDR _AC(0x0000000010000000,UL)41 #define MODULES_LEN _AC(0x00000000e0000000,UL)42 #define MODULES_END _AC(0x00000000f0000000,UL)43 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)44 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)45 #define VMALLOC_START _AC(0x0000000100000000,UL)52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)[all …]
11 #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))22 #define CTX_PGSZ_8KB _AC(0x0,UL)23 #define CTX_PGSZ_64KB _AC(0x1,UL)24 #define CTX_PGSZ_512KB _AC(0x2,UL)25 #define CTX_PGSZ_4MB _AC(0x3,UL)26 #define CTX_PGSZ_BITS _AC(0x7,UL)
9 #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)25 #define REAL_HPAGE_SIZE (_AC(1,UL) << REAL_HPAGE_SHIFT)28 #define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)32 #define REAL_HPAGE_PER_HPAGE (_AC(1,UL) << (HPAGE_SHIFT - REAL_HPAGE_SHIFT))127 _AC(0x0000000070000000,UL) : \
20 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */21 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */22 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */23 #define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */25 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */26 #define SR_FS_OFF _AC(0x00000000, UL)27 #define SR_FS_INITIAL _AC(0x00002000, UL)28 #define SR_FS_CLEAN _AC(0x00004000, UL)29 #define SR_FS_DIRTY _AC(0x00006000, UL)31 #define SR_XS _AC(0x00018000, UL) /* Extension Status */[all …]
21 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)26 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
24 #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)32 #define PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL)
24 # define PHYS_OFFSET _AC(0, UL)30 #define CAC_BASE _AC(0x40000000, UL)32 #define CAC_BASE _AC(0x80000000, UL)35 #define IO_BASE _AC(0xa0000000, UL)38 #define UNCAC_BASE _AC(0xa0000000, UL)43 #define MAP_BASE _AC(0x60000000, UL)45 #define MAP_BASE _AC(0xc0000000, UL)53 #define HIGHMEM_START _AC(0x20000000, UL)65 #define IO_BASE _AC(0x9000000000000000, UL)69 #define UNCAC_BASE _AC(0x9000000000000000, UL)[all …]
136 #define KVM_PHYS_SIZE (_AC(1, ULL) << KVM_PHYS_SHIFT)137 #define KVM_PHYS_MASK (KVM_PHYS_SIZE - _AC(1, ULL))138 #define PTRS_PER_S2_PGD (_AC(1, ULL) << (KVM_PHYS_SHIFT - 30))164 #define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_X)165 #define VTTBR_VMID_SHIFT _AC(48, ULL)170 #define HSR_EC (_AC(0x3f, UL) << HSR_EC_SHIFT)171 #define HSR_IL (_AC(1, UL) << 25)174 #define HSR_ISV (_AC(1, UL) << HSR_ISV_SHIFT)182 #define HSR_CV (_AC(1, UL) << HSR_CV_SHIFT)184 #define HSR_COND (_AC(0xf, UL) << HSR_COND_SHIFT)[all …]
64 #define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)98 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)100 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)102 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)143 #define MODULES_END _AC(0xffffffffff000000, UL)146 #define ESPFIX_PGD_ENTRY _AC(-2, UL)149 #define CPU_ENTRY_AREA_PGD _AC(-4, UL)152 #define EFI_VA_START ( -4 * (_AC(1, UL) << 30))153 #define EFI_VA_END (-68 * (_AC(1, UL) << 30))
11 #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)14 #define PMD_PAGE_SIZE (_AC(1, UL) << PMD_SHIFT)17 #define PUD_PAGE_SIZE (_AC(1, UL) << PUD_SHIFT)30 #define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
40 #define __PAGE_OFFSET_BASE_L5 _AC(0xff10000000000000, UL)41 #define __PAGE_OFFSET_BASE_L4 _AC(0xffff880000000000, UL)49 #define __START_KERNEL_map _AC(0xffffffff80000000, UL)
13 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \14 (((flags) & _AC(0x0000f0ff,ULL)) << 40) | \15 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \16 (((base) & _AC(0x00ffffff,ULL)) << 16) | \17 (((limit) & _AC(0x0000ffff,ULL))))
17 #define _AC(X,Y) X macro21 #define _AC(X,Y) __AC(X,Y) macro25 #define _UL(x) (_AC(x, UL))26 #define _ULL(x) (_AC(x, ULL))
15 #define CAC_BASE _AC(0x8000000000000000, UL)16 #define UNCAC_BASE _AC(0x8000000000000000, UL)17 #define IO_BASE _AC(0x8000000000000000, UL)
36 #define PAGE_OFFSET _AC(0x0, UL)37 #define PHYS_OFFSET _AC(0x80000000, UL)38 #define HIGHMEM_START _AC(0xffff0000, UL)
17 #define PAGE_OFFSET _AC(0x94000000, UL)18 #define PHYS_OFFSET _AC(0x14000000, UL)
28 #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)31 #define CONT_SIZE (_AC(1, UL) << (CONT_SHIFT + PAGE_SHIFT))
58 #define S2_PGDIR_SIZE (_AC(1, UL) << S2_PGDIR_SHIFT)77 #define S2_PUD_SIZE (_AC(1, UL) << S2_PUD_SHIFT)102 #define S2_PMD_SIZE (_AC(1, UL) << S2_PMD_SHIFT)
61 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)71 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)81 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)89 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
32 #define X86_EFLAGS_IOPL (_AC(3,UL) << X86_EFLAGS_IOPL_BIT)83 #define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL))137 #define X86_CR8_TPR _AC(0x0000000f,UL) /* task priority register */
14 #define PHYS_OFFSET _AC(0x20000000, UL)
