1 /*
2 * PHY support for Xenon SDHC
3 *
4 * Copyright (C) 2016 Marvell, All Rights Reserved.
5 *
6 * Author: Hu Ziji <huziji@marvell.com>
7 * Date: 2016-8-24
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 */
13
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/ktime.h>
17 #include <linux/of_address.h>
18
19 #include "sdhci-pltfm.h"
20 #include "sdhci-xenon.h"
21
22 /* Register base for eMMC PHY 5.0 Version */
23 #define XENON_EMMC_5_0_PHY_REG_BASE 0x0160
24 /* Register base for eMMC PHY 5.1 Version */
25 #define XENON_EMMC_PHY_REG_BASE 0x0170
26
27 #define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE
28 #define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE
29 #define XENON_TIMING_ADJUST_SLOW_MODE BIT(29)
30 #define XENON_TIMING_ADJUST_SDIO_MODE BIT(28)
31 #define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18)
32 #define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
33 #define XENON_PHY_INITIALIZAION BIT(31)
34 #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF
35 #define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12
36 #define XENON_FC_SYNC_EN_DURATION_MASK 0xF
37 #define XENON_FC_SYNC_EN_DURATION_SHIFT 8
38 #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF
39 #define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4
40 #define XENON_FC_SYNC_RST_DURATION_MASK 0xF
41 #define XENON_FC_SYNC_RST_DURATION_SHIFT 0
42
43 #define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4)
44 #define XENON_EMMC_5_0_PHY_FUNC_CONTROL \
45 (XENON_EMMC_5_0_PHY_REG_BASE + 0x4)
46 #define XENON_ASYNC_DDRMODE_MASK BIT(23)
47 #define XENON_ASYNC_DDRMODE_SHIFT 23
48 #define XENON_CMD_DDR_MODE BIT(16)
49 #define XENON_DQ_DDR_MODE_SHIFT 8
50 #define XENON_DQ_DDR_MODE_MASK 0xFF
51 #define XENON_DQ_ASYNC_MODE BIT(4)
52
53 #define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8)
54 #define XENON_EMMC_5_0_PHY_PAD_CONTROL \
55 (XENON_EMMC_5_0_PHY_REG_BASE + 0x8)
56 #define XENON_REC_EN_SHIFT 24
57 #define XENON_REC_EN_MASK 0xF
58 #define XENON_FC_DQ_RECEN BIT(24)
59 #define XENON_FC_CMD_RECEN BIT(25)
60 #define XENON_FC_QSP_RECEN BIT(26)
61 #define XENON_FC_QSN_RECEN BIT(27)
62 #define XENON_OEN_QSN BIT(28)
63 #define XENON_AUTO_RECEN_CTRL BIT(30)
64 #define XENON_FC_ALL_CMOS_RECEIVER 0xF000
65
66 #define XENON_EMMC5_FC_QSP_PD BIT(18)
67 #define XENON_EMMC5_FC_QSP_PU BIT(22)
68 #define XENON_EMMC5_FC_CMD_PD BIT(17)
69 #define XENON_EMMC5_FC_CMD_PU BIT(21)
70 #define XENON_EMMC5_FC_DQ_PD BIT(16)
71 #define XENON_EMMC5_FC_DQ_PU BIT(20)
72
73 #define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC)
74 #define XENON_EMMC5_1_FC_QSP_PD BIT(9)
75 #define XENON_EMMC5_1_FC_QSP_PU BIT(25)
76 #define XENON_EMMC5_1_FC_CMD_PD BIT(8)
77 #define XENON_EMMC5_1_FC_CMD_PU BIT(24)
78 #define XENON_EMMC5_1_FC_DQ_PD 0xFF
79 #define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16)
80
81 #define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10)
82 #define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \
83 (XENON_EMMC_5_0_PHY_REG_BASE + 0xC)
84 #define XENON_ZNR_MASK 0x1F
85 #define XENON_ZNR_SHIFT 8
86 #define XENON_ZPR_MASK 0x1F
87 /* Preferred ZNR and ZPR value vary between different boards.
88 * The specific ZNR and ZPR value should be defined here
89 * according to board actual timing.
90 */
91 #define XENON_ZNR_DEF_VALUE 0xF
92 #define XENON_ZPR_DEF_VALUE 0xF
93
94 #define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14)
95 #define XENON_EMMC_5_0_PHY_DLL_CONTROL \
96 (XENON_EMMC_5_0_PHY_REG_BASE + 0x10)
97 #define XENON_DLL_ENABLE BIT(31)
98 #define XENON_DLL_UPDATE_STROBE_5_0 BIT(30)
99 #define XENON_DLL_REFCLK_SEL BIT(30)
100 #define XENON_DLL_UPDATE BIT(23)
101 #define XENON_DLL_PHSEL1_SHIFT 24
102 #define XENON_DLL_PHSEL0_SHIFT 16
103 #define XENON_DLL_PHASE_MASK 0x3F
104 #define XENON_DLL_PHASE_90_DEGREE 0x1F
105 #define XENON_DLL_FAST_LOCK BIT(5)
106 #define XENON_DLL_GAIN2X BIT(3)
107 #define XENON_DLL_BYPASS_EN BIT(0)
108
109 #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \
110 (XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
111 #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54
112 #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
113 #define XENON_LOGIC_TIMING_VALUE 0x00AA8977
114
115 /*
116 * List offset of PHY registers and some special register values
117 * in eMMC PHY 5.0 or eMMC PHY 5.1
118 */
119 struct xenon_emmc_phy_regs {
120 /* Offset of Timing Adjust register */
121 u16 timing_adj;
122 /* Offset of Func Control register */
123 u16 func_ctrl;
124 /* Offset of Pad Control register */
125 u16 pad_ctrl;
126 /* Offset of Pad Control register 2 */
127 u16 pad_ctrl2;
128 /* Offset of DLL Control register */
129 u16 dll_ctrl;
130 /* Offset of Logic Timing Adjust register */
131 u16 logic_timing_adj;
132 /* DLL Update Enable bit */
133 u32 dll_update;
134 /* value in Logic Timing Adjustment register */
135 u32 logic_timing_val;
136 };
137
138 static const char * const phy_types[] = {
139 "emmc 5.0 phy",
140 "emmc 5.1 phy"
141 };
142
143 enum xenon_phy_type_enum {
144 EMMC_5_0_PHY,
145 EMMC_5_1_PHY,
146 NR_PHY_TYPES
147 };
148
149 enum soc_pad_ctrl_type {
150 SOC_PAD_SD,
151 SOC_PAD_FIXED_1_8V,
152 };
153
154 struct soc_pad_ctrl {
155 /* Register address of SoC PHY PAD ctrl */
156 void __iomem *reg;
157 /* SoC PHY PAD ctrl type */
158 enum soc_pad_ctrl_type pad_type;
159 /* SoC specific operation to set SoC PHY PAD */
160 void (*set_soc_pad)(struct sdhci_host *host,
161 unsigned char signal_voltage);
162 };
163
164 static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
165 .timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST,
166 .func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL,
167 .pad_ctrl = XENON_EMMC_5_0_PHY_PAD_CONTROL,
168 .pad_ctrl2 = XENON_EMMC_5_0_PHY_PAD_CONTROL2,
169 .dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL,
170 .logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
171 .dll_update = XENON_DLL_UPDATE_STROBE_5_0,
172 .logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE,
173 };
174
175 static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
176 .timing_adj = XENON_EMMC_PHY_TIMING_ADJUST,
177 .func_ctrl = XENON_EMMC_PHY_FUNC_CONTROL,
178 .pad_ctrl = XENON_EMMC_PHY_PAD_CONTROL,
179 .pad_ctrl2 = XENON_EMMC_PHY_PAD_CONTROL2,
180 .dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL,
181 .logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
182 .dll_update = XENON_DLL_UPDATE,
183 .logic_timing_val = XENON_LOGIC_TIMING_VALUE,
184 };
185
186 /*
187 * eMMC PHY configuration and operations
188 */
189 struct xenon_emmc_phy_params {
190 bool slow_mode;
191
192 u8 znr;
193 u8 zpr;
194
195 /* Nr of consecutive Sampling Points of a Valid Sampling Window */
196 u8 nr_tun_times;
197 /* Divider for calculating Tuning Step */
198 u8 tun_step_divider;
199
200 struct soc_pad_ctrl pad_ctrl;
201 };
202
xenon_alloc_emmc_phy(struct sdhci_host * host)203 static int xenon_alloc_emmc_phy(struct sdhci_host *host)
204 {
205 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
206 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
207 struct xenon_emmc_phy_params *params;
208
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL);
210 if (!params)
211 return -ENOMEM;
212
213 priv->phy_params = params;
214 if (priv->phy_type == EMMC_5_0_PHY)
215 priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs;
216 else
217 priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs;
218
219 return 0;
220 }
221
222 /*
223 * eMMC 5.0/5.1 PHY init/re-init.
224 * eMMC PHY init should be executed after:
225 * 1. SDCLK frequency changes.
226 * 2. SDCLK is stopped and re-enabled.
227 * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
228 * are changed
229 */
xenon_emmc_phy_init(struct sdhci_host * host)230 static int xenon_emmc_phy_init(struct sdhci_host *host)
231 {
232 u32 reg;
233 u32 wait, clock;
234 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
235 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
236 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
237
238 reg = sdhci_readl(host, phy_regs->timing_adj);
239 reg |= XENON_PHY_INITIALIZAION;
240 sdhci_writel(host, reg, phy_regs->timing_adj);
241
242 /* Add duration of FC_SYNC_RST */
243 wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) &
244 XENON_FC_SYNC_RST_DURATION_MASK);
245 /* Add interval between FC_SYNC_EN and FC_SYNC_RST */
246 wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) &
247 XENON_FC_SYNC_RST_EN_DURATION_MASK);
248 /* Add duration of asserting FC_SYNC_EN */
249 wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) &
250 XENON_FC_SYNC_EN_DURATION_MASK);
251 /* Add duration of waiting for PHY */
252 wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) &
253 XENON_WAIT_CYCLE_BEFORE_USING_MASK);
254 /* 4 additional bus clock and 4 AXI bus clock are required */
255 wait += 8;
256 wait <<= 20;
257
258 clock = host->clock;
259 if (!clock)
260 /* Use the possibly slowest bus frequency value */
261 clock = XENON_LOWEST_SDCLK_FREQ;
262 /* get the wait time */
263 wait /= clock;
264 wait++;
265 /* wait for host eMMC PHY init completes */
266 udelay(wait);
267
268 reg = sdhci_readl(host, phy_regs->timing_adj);
269 reg &= XENON_PHY_INITIALIZAION;
270 if (reg) {
271 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
272 wait);
273 return -ETIMEDOUT;
274 }
275
276 return 0;
277 }
278
279 #define ARMADA_3700_SOC_PAD_1_8V 0x1
280 #define ARMADA_3700_SOC_PAD_3_3V 0x0
281
armada_3700_soc_pad_voltage_set(struct sdhci_host * host,unsigned char signal_voltage)282 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
283 unsigned char signal_voltage)
284 {
285 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
286 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
287 struct xenon_emmc_phy_params *params = priv->phy_params;
288
289 if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) {
290 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
291 } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) {
292 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
293 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
294 else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
295 writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);
296 }
297 }
298
299 /*
300 * Set SoC PHY voltage PAD control register,
301 * according to the operation voltage on PAD.
302 * The detailed operation depends on SoC implementation.
303 */
xenon_emmc_phy_set_soc_pad(struct sdhci_host * host,unsigned char signal_voltage)304 static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host,
305 unsigned char signal_voltage)
306 {
307 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
308 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
309 struct xenon_emmc_phy_params *params = priv->phy_params;
310
311 if (!params->pad_ctrl.reg)
312 return;
313
314 if (params->pad_ctrl.set_soc_pad)
315 params->pad_ctrl.set_soc_pad(host, signal_voltage);
316 }
317
318 /*
319 * Enable eMMC PHY HW DLL
320 * DLL should be enabled and stable before HS200/SDR104 tuning,
321 * and before HS400 data strobe setting.
322 */
xenon_emmc_phy_enable_dll(struct sdhci_host * host)323 static int xenon_emmc_phy_enable_dll(struct sdhci_host *host)
324 {
325 u32 reg;
326 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
327 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
328 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
329 ktime_t timeout;
330
331 if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
332 return -EINVAL;
333
334 reg = sdhci_readl(host, phy_regs->dll_ctrl);
335 if (reg & XENON_DLL_ENABLE)
336 return 0;
337
338 /* Enable DLL */
339 reg = sdhci_readl(host, phy_regs->dll_ctrl);
340 reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK);
341
342 /*
343 * Set Phase as 90 degree, which is most common value.
344 * Might set another value if necessary.
345 * The granularity is 1 degree.
346 */
347 reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) |
348 (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT));
349 reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) |
350 (XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT));
351
352 reg &= ~XENON_DLL_BYPASS_EN;
353 reg |= phy_regs->dll_update;
354 if (priv->phy_type == EMMC_5_1_PHY)
355 reg &= ~XENON_DLL_REFCLK_SEL;
356 sdhci_writel(host, reg, phy_regs->dll_ctrl);
357
358 /* Wait max 32 ms */
359 timeout = ktime_add_ms(ktime_get(), 32);
360 while (!(sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
361 XENON_DLL_LOCK_STATE)) {
362 if (ktime_after(ktime_get(), timeout)) {
363 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
364 return -ETIMEDOUT;
365 }
366 udelay(100);
367 }
368 return 0;
369 }
370
371 /*
372 * Config to eMMC PHY to prepare for tuning.
373 * Enable HW DLL and set the TUNING_STEP
374 */
xenon_emmc_phy_config_tuning(struct sdhci_host * host)375 static int xenon_emmc_phy_config_tuning(struct sdhci_host *host)
376 {
377 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
378 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
379 struct xenon_emmc_phy_params *params = priv->phy_params;
380 u32 reg, tuning_step;
381 int ret;
382
383 if (host->clock <= MMC_HIGH_52_MAX_DTR)
384 return -EINVAL;
385
386 ret = xenon_emmc_phy_enable_dll(host);
387 if (ret)
388 return ret;
389
390 /* Achieve TUNING_STEP with HW DLL help */
391 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);
392 tuning_step = reg / params->tun_step_divider;
393 if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) {
394 dev_warn(mmc_dev(host->mmc),
395 "HS200 TUNING_STEP %d is larger than MAX value\n",
396 tuning_step);
397 tuning_step = XENON_TUNING_STEP_MASK;
398 }
399
400 /* Set TUNING_STEP for later tuning */
401 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);
402 reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK <<
403 XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
404 reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
405 reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT);
406 reg |= (tuning_step << XENON_TUNING_STEP_SHIFT);
407 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);
408
409 return 0;
410 }
411
xenon_emmc_phy_disable_strobe(struct sdhci_host * host)412 static void xenon_emmc_phy_disable_strobe(struct sdhci_host *host)
413 {
414 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
415 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
416 u32 reg;
417
418 /* Disable both SDHC Data Strobe and Enhanced Strobe */
419 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
420 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);
421 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
422
423 /* Clear Strobe line Pull down or Pull up */
424 if (priv->phy_type == EMMC_5_0_PHY) {
425 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
426 reg &= ~(XENON_EMMC5_FC_QSP_PD | XENON_EMMC5_FC_QSP_PU);
427 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
428 } else {
429 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
430 reg &= ~(XENON_EMMC5_1_FC_QSP_PD | XENON_EMMC5_1_FC_QSP_PU);
431 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
432 }
433 }
434
435 /* Set HS400 Data Strobe and Enhanced Strobe */
xenon_emmc_phy_strobe_delay_adj(struct sdhci_host * host)436 static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host)
437 {
438 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
439 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
440 u32 reg;
441
442 if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
443 return;
444
445 if (host->clock <= MMC_HIGH_52_MAX_DTR)
446 return;
447
448 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
449
450 xenon_emmc_phy_enable_dll(host);
451
452 /* Enable SDHC Data Strobe */
453 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
454 reg |= XENON_ENABLE_DATA_STROBE;
455 /*
456 * Enable SDHC Enhanced Strobe if supported
457 * Xenon Enhanced Strobe should be enabled only when
458 * 1. card is in HS400 mode and
459 * 2. SDCLK is higher than 52MHz
460 * 3. DLL is enabled
461 */
462 if (host->mmc->ios.enhanced_strobe)
463 reg |= XENON_ENABLE_RESP_STROBE;
464 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
465
466 /* Set Data Strobe Pull down */
467 if (priv->phy_type == EMMC_5_0_PHY) {
468 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
469 reg |= XENON_EMMC5_FC_QSP_PD;
470 reg &= ~XENON_EMMC5_FC_QSP_PU;
471 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
472 } else {
473 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
474 reg |= XENON_EMMC5_1_FC_QSP_PD;
475 reg &= ~XENON_EMMC5_1_FC_QSP_PU;
476 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
477 }
478 }
479
480 /*
481 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
482 * in SDR mode, enable Slow Mode to bypass eMMC PHY.
483 * SDIO slower SDR mode also requires Slow Mode.
484 *
485 * If Slow Mode is enabled, return true.
486 * Otherwise, return false.
487 */
xenon_emmc_phy_slow_mode(struct sdhci_host * host,unsigned char timing)488 static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host,
489 unsigned char timing)
490 {
491 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
492 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
493 struct xenon_emmc_phy_params *params = priv->phy_params;
494 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
495 u32 reg;
496 int ret;
497
498 if (host->clock > MMC_HIGH_52_MAX_DTR)
499 return false;
500
501 reg = sdhci_readl(host, phy_regs->timing_adj);
502 /* When in slower SDR mode, enable Slow Mode for SDIO
503 * or when Slow Mode flag is set
504 */
505 switch (timing) {
506 case MMC_TIMING_LEGACY:
507 /*
508 * If Slow Mode is required, enable Slow Mode by default
509 * in early init phase to avoid any potential issue.
510 */
511 if (params->slow_mode) {
512 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
513 ret = true;
514 } else {
515 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
516 ret = false;
517 }
518 break;
519 case MMC_TIMING_UHS_SDR25:
520 case MMC_TIMING_UHS_SDR12:
521 case MMC_TIMING_SD_HS:
522 case MMC_TIMING_MMC_HS:
523 if ((priv->init_card_type == MMC_TYPE_SDIO) ||
524 params->slow_mode) {
525 reg |= XENON_TIMING_ADJUST_SLOW_MODE;
526 ret = true;
527 break;
528 }
529 /* else: fall through */
530 default:
531 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
532 ret = false;
533 }
534
535 sdhci_writel(host, reg, phy_regs->timing_adj);
536 return ret;
537 }
538
539 /*
540 * Set-up eMMC 5.0/5.1 PHY.
541 * Specific configuration depends on the current speed mode in use.
542 */
xenon_emmc_phy_set(struct sdhci_host * host,unsigned char timing)543 static void xenon_emmc_phy_set(struct sdhci_host *host,
544 unsigned char timing)
545 {
546 u32 reg;
547 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
548 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
549 struct xenon_emmc_phy_params *params = priv->phy_params;
550 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
551
552 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
553
554 /* Setup pad, set bit[28] and bits[26:24] */
555 reg = sdhci_readl(host, phy_regs->pad_ctrl);
556 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
557 XENON_FC_QSP_RECEN | XENON_OEN_QSN);
558 /* All FC_XX_RECEIVCE should be set as CMOS Type */
559 reg |= XENON_FC_ALL_CMOS_RECEIVER;
560 sdhci_writel(host, reg, phy_regs->pad_ctrl);
561
562 /* Set CMD and DQ Pull Up */
563 if (priv->phy_type == EMMC_5_0_PHY) {
564 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
565 reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU);
566 reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD);
567 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
568 } else {
569 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
570 reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU);
571 reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD);
572 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
573 }
574
575 if (timing == MMC_TIMING_LEGACY) {
576 xenon_emmc_phy_slow_mode(host, timing);
577 goto phy_init;
578 }
579
580 /*
581 * If SDIO card, set SDIO Mode
582 * Otherwise, clear SDIO Mode
583 */
584 reg = sdhci_readl(host, phy_regs->timing_adj);
585 if (priv->init_card_type == MMC_TYPE_SDIO)
586 reg |= XENON_TIMING_ADJUST_SDIO_MODE;
587 else
588 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
589 sdhci_writel(host, reg, phy_regs->timing_adj);
590
591 if (xenon_emmc_phy_slow_mode(host, timing))
592 goto phy_init;
593
594 /*
595 * Set preferred ZNR and ZPR value
596 * The ZNR and ZPR value vary between different boards.
597 * Define them both in sdhci-xenon-emmc-phy.h.
598 */
599 reg = sdhci_readl(host, phy_regs->pad_ctrl2);
600 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
601 reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr);
602 sdhci_writel(host, reg, phy_regs->pad_ctrl2);
603
604 /*
605 * When setting EMMC_PHY_FUNC_CONTROL register,
606 * SD clock should be disabled
607 */
608 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
609 reg &= ~SDHCI_CLOCK_CARD_EN;
610 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
611
612 reg = sdhci_readl(host, phy_regs->func_ctrl);
613 switch (timing) {
614 case MMC_TIMING_MMC_HS400:
615 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
616 XENON_CMD_DDR_MODE;
617 reg &= ~XENON_DQ_ASYNC_MODE;
618 break;
619 case MMC_TIMING_UHS_DDR50:
620 case MMC_TIMING_MMC_DDR52:
621 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
622 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;
623 break;
624 default:
625 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
626 XENON_CMD_DDR_MODE);
627 reg |= XENON_DQ_ASYNC_MODE;
628 }
629 sdhci_writel(host, reg, phy_regs->func_ctrl);
630
631 /* Enable bus clock */
632 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
633 reg |= SDHCI_CLOCK_CARD_EN;
634 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
635
636 if (timing == MMC_TIMING_MMC_HS400)
637 /* Hardware team recommend a value for HS400 */
638 sdhci_writel(host, phy_regs->logic_timing_val,
639 phy_regs->logic_timing_adj);
640 else
641 xenon_emmc_phy_disable_strobe(host);
642
643 phy_init:
644 xenon_emmc_phy_init(host);
645
646 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
647 }
648
get_dt_pad_ctrl_data(struct sdhci_host * host,struct device_node * np,struct xenon_emmc_phy_params * params)649 static int get_dt_pad_ctrl_data(struct sdhci_host *host,
650 struct device_node *np,
651 struct xenon_emmc_phy_params *params)
652 {
653 int ret = 0;
654 const char *name;
655 struct resource iomem;
656
657 if (of_device_is_compatible(np, "marvell,armada-3700-sdhci"))
658 params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set;
659 else
660 return 0;
661
662 if (of_address_to_resource(np, 1, &iomem)) {
663 dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %s\n",
664 np->name);
665 return -EINVAL;
666 }
667
668 params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
669 &iomem);
670 if (IS_ERR(params->pad_ctrl.reg))
671 return PTR_ERR(params->pad_ctrl.reg);
672
673 ret = of_property_read_string(np, "marvell,pad-type", &name);
674 if (ret) {
675 dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n");
676 return ret;
677 }
678 if (!strcmp(name, "sd")) {
679 params->pad_ctrl.pad_type = SOC_PAD_SD;
680 } else if (!strcmp(name, "fixed-1-8v")) {
681 params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V;
682 } else {
683 dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n",
684 name);
685 return -EINVAL;
686 }
687
688 return ret;
689 }
690
xenon_emmc_phy_parse_param_dt(struct sdhci_host * host,struct device_node * np,struct xenon_emmc_phy_params * params)691 static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host,
692 struct device_node *np,
693 struct xenon_emmc_phy_params *params)
694 {
695 u32 value;
696
697 params->slow_mode = false;
698 if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
699 params->slow_mode = true;
700
701 params->znr = XENON_ZNR_DEF_VALUE;
702 if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
703 params->znr = value & XENON_ZNR_MASK;
704
705 params->zpr = XENON_ZPR_DEF_VALUE;
706 if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
707 params->zpr = value & XENON_ZPR_MASK;
708
709 params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;
710 if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
711 &value))
712 params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;
713
714 params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
715 if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
716 &value))
717 params->tun_step_divider = value & 0xFF;
718
719 return get_dt_pad_ctrl_data(host, np, params);
720 }
721
722 /* Set SoC PHY Voltage PAD */
xenon_soc_pad_ctrl(struct sdhci_host * host,unsigned char signal_voltage)723 void xenon_soc_pad_ctrl(struct sdhci_host *host,
724 unsigned char signal_voltage)
725 {
726 xenon_emmc_phy_set_soc_pad(host, signal_voltage);
727 }
728
729 /*
730 * Setting PHY when card is working in High Speed Mode.
731 * HS400 set Data Strobe and Enhanced Strobe if it is supported.
732 * HS200/SDR104 set tuning config to prepare for tuning.
733 */
xenon_hs_delay_adj(struct sdhci_host * host)734 static int xenon_hs_delay_adj(struct sdhci_host *host)
735 {
736 int ret = 0;
737
738 if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
739 return -EINVAL;
740
741 switch (host->timing) {
742 case MMC_TIMING_MMC_HS400:
743 xenon_emmc_phy_strobe_delay_adj(host);
744 return 0;
745 case MMC_TIMING_MMC_HS200:
746 case MMC_TIMING_UHS_SDR104:
747 return xenon_emmc_phy_config_tuning(host);
748 case MMC_TIMING_MMC_DDR52:
749 case MMC_TIMING_UHS_DDR50:
750 /*
751 * DDR Mode requires driver to scan Sampling Fixed Delay Line,
752 * to find out a perfect operation sampling point.
753 * It is hard to implement such a scan in host driver
754 * since initiating commands by host driver is not safe.
755 * Thus so far just keep PHY Sampling Fixed Delay in
756 * default value of DDR mode.
757 *
758 * If any timing issue occurs in DDR mode on Marvell products,
759 * please contact maintainer for internal support in Marvell.
760 */
761 dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
762 return 0;
763 }
764
765 return ret;
766 }
767
768 /*
769 * Adjust PHY setting.
770 * PHY setting should be adjusted when SDCLK frequency, Bus Width
771 * or Speed Mode is changed.
772 * Additional config are required when card is working in High Speed mode,
773 * after leaving Legacy Mode.
774 */
xenon_phy_adj(struct sdhci_host * host,struct mmc_ios * ios)775 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
776 {
777 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
778 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
779 int ret = 0;
780
781 if (!host->clock) {
782 priv->clock = 0;
783 return 0;
784 }
785
786 /*
787 * The timing, frequency or bus width is changed,
788 * better to set eMMC PHY based on current setting
789 * and adjust Xenon SDHC delay.
790 */
791 if ((host->clock == priv->clock) &&
792 (ios->bus_width == priv->bus_width) &&
793 (ios->timing == priv->timing))
794 return 0;
795
796 xenon_emmc_phy_set(host, ios->timing);
797
798 /* Update the record */
799 priv->bus_width = ios->bus_width;
800
801 priv->timing = ios->timing;
802 priv->clock = host->clock;
803
804 /* Legacy mode is a special case */
805 if (ios->timing == MMC_TIMING_LEGACY)
806 return 0;
807
808 if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
809 ret = xenon_hs_delay_adj(host);
810 return ret;
811 }
812
xenon_add_phy(struct device_node * np,struct sdhci_host * host,const char * phy_name)813 static int xenon_add_phy(struct device_node *np, struct sdhci_host *host,
814 const char *phy_name)
815 {
816 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
817 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
818 int ret;
819
820 priv->phy_type = match_string(phy_types, NR_PHY_TYPES, phy_name);
821 if (priv->phy_type < 0) {
822 dev_err(mmc_dev(host->mmc),
823 "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
824 phy_name);
825 priv->phy_type = EMMC_5_1_PHY;
826 }
827
828 ret = xenon_alloc_emmc_phy(host);
829 if (ret)
830 return ret;
831
832 return xenon_emmc_phy_parse_param_dt(host, np, priv->phy_params);
833 }
834
xenon_phy_parse_dt(struct device_node * np,struct sdhci_host * host)835 int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
836 {
837 const char *phy_type = NULL;
838
839 if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
840 return xenon_add_phy(np, host, phy_type);
841
842 return xenon_add_phy(np, host, "emmc 5.1 phy");
843 }
844
