Searched refs:WRITE_DATA_DST_SEL (Results 1 – 13 of 13) sorted by relevance
133 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
110 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
144 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
262 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
903 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5457 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5465 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5473 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5481 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6608 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6617 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7463 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7496 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
309 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()408 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()4175 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()4184 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()4208 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()4230 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
3260 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4185 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4193 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4201 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4209 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
2365 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3752 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5695 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5709 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5738 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5078 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5093 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5101 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
