| /Linux-v4.19/drivers/gpu/drm/mgag200/ |
| D | mgag200_mode.c | 43 WREG8(DAC_INDEX + MGA1064_INDEX, 0); in mga_crtc_load_lut()
63 WREG8(DAC_INDEX + MGA1064_COL_PAL, r); in mga_crtc_load_lut()
64 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); in mga_crtc_load_lut()
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, b); in mga_crtc_load_lut()
71 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8); in mga_crtc_load_lut()
72 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); in mga_crtc_load_lut()
73 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8); in mga_crtc_load_lut()
306 WREG8(MGAREG_CRTC_INDEX, 0x1e); in mga_g200wb_set_plls()
309 WREG8(MGAREG_CRTC_DATA, tmp+1); in mga_g200wb_set_plls()
313 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mga_g200wb_set_plls()
[all …]
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| D | mgag200_cursor.c | 23 WREG8(MGA_CURPOSXL, 0); in mga_hide_cursor()
24 WREG8(MGA_CURPOSXH, 0); in mga_hide_cursor()
58 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
59 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
64 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
65 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
84 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
85 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
90 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
91 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
[all …]
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| D | mgag200_drv.h | 46 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) macro
56 WREG8(ATTR_INDEX, reg); \
57 WREG8(ATTR_DATA, v); \
62 WREG8(MGAREG_SEQ_INDEX, reg); \
63 WREG8(MGAREG_SEQ_DATA, v); \
68 WREG8(MGAREG_CRTC_INDEX, reg); \
69 WREG8(MGAREG_CRTC_DATA, v); \
75 WREG8(MGAREG_CRTCEXT_INDEX, reg); \
76 WREG8(MGAREG_CRTCEXT_DATA, v); \
84 WREG8(GFX_INDEX, reg); \
[all …]
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| D | mgag200_i2c.c | 37 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); in mga_i2c_read_gpio()
45 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); in mga_i2c_set_gpio()
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| /Linux-v4.19/drivers/gpu/drm/cirrus/ |
| D | cirrus_drv.h | 40 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)cdev->rmmio) + (reg)) macro
49 WREG8(SEQ_INDEX, reg); \
50 WREG8(SEQ_DATA, v); \
58 WREG8(CRT_INDEX, reg); \
59 WREG8(CRT_DATA, v); \
67 WREG8(GFX_INDEX, reg); \
68 WREG8(GFX_DATA, v); \
84 WREG8(VGA_DAC_MASK, v); \
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| D | cirrus_mode.c | 66 WREG8(SEQ_INDEX, 0x1); in cirrus_crtc_dpms()
70 WREG8(GFX_INDEX, 0xe); in cirrus_crtc_dpms()
85 WREG8(CRT_INDEX, 0x1b); in cirrus_set_start_address()
91 WREG8(CRT_INDEX, 0x1d); in cirrus_set_start_address()
232 WREG8(SEQ_INDEX, 0x7); in cirrus_crtc_mode_set()
307 WREG8(PALETTE_INDEX, i); in cirrus_crtc_load_lut()
308 WREG8(PALETTE_DATA, *r++ >> 8); in cirrus_crtc_load_lut()
309 WREG8(PALETTE_DATA, *g++ >> 8); in cirrus_crtc_load_lut()
310 WREG8(PALETTE_DATA, *b++ >> 8); in cirrus_crtc_load_lut()
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| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | mxgpu_ai.c | 36 WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); in xgpu_ai_mailbox_send_ack()
41 WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); in xgpu_ai_mailbox_set_valid()
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| D | amdgpu.h | 1596 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) macro
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| /Linux-v4.19/drivers/gpu/drm/radeon/ |
| D | radeon_legacy_tv.c | 287 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
289 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); in radeon_wait_pll_lock()
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| D | r100.c | 2880 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2893 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
3784 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3815 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3828 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); in r100_vga_render_disable()
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| D | radeon_display.c | 65 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); in avivo_crtc_load_lut()
200 WREG8(RADEON_PALETTE_INDEX, 0); in legacy_crtc_load_lut()
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| D | radeon.h | 2517 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) macro
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