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Searched refs:WREG32_SOC15 (Results 1 – 20 of 20) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dmmhub_v1_0.c58 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v1_0_init_gart_pt_regs()
61 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v1_0_init_gart_pt_regs()
69 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
71 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
86 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); in mmhub_v1_0_init_system_aperture_regs()
87 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); in mmhub_v1_0_init_system_aperture_regs()
88 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); in mmhub_v1_0_init_system_aperture_regs()
91 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v1_0_init_system_aperture_regs()
[all …]
Dgfxhub_v1_0.c48 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_init_gart_pt_regs()
51 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_init_gart_pt_regs()
59 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
61 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
64 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
66 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
75 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
76 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); in gfxhub_v1_0_init_system_aperture_regs()
77 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); in gfxhub_v1_0_init_system_aperture_regs()
80 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
[all …]
Dvcn_v1_0.c281 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume()
283 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume()
285 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v1_0_mc_resume()
288 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume()
290 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume()
293 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume()
297 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v1_0_mc_resume()
299 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v1_0_mc_resume()
301 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume()
303 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v1_0_mc_resume()
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Duvd_v7_0.c140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
666 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
668 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
672 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
674 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
679 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, in uvd_v7_0_mc_resume()
681 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v7_0_mc_resume()
683 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
[all …]
Dvega10_ih.c51 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_enable_interrupts()
68 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_disable_interrupts()
70 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); in vega10_ih_disable_interrupts()
71 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); in vega10_ih_disable_interrupts()
103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); in vega10_ih_irq_init()
104 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); in vega10_ih_irq_init()
107 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in vega10_ih_irq_init()
108 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff); in vega10_ih_irq_init()
124 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_irq_init()
131 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); in vega10_ih_irq_init()
[all …]
Dgfx_v9_0.c813 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); in gfx_v9_0_init_lbpw()
814 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); in gfx_v9_0_init_lbpw()
815 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); in gfx_v9_0_init_lbpw()
816 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); in gfx_v9_0_init_lbpw()
819 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); in gfx_v9_0_init_lbpw()
822 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); in gfx_v9_0_init_lbpw()
827 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); in gfx_v9_0_init_lbpw()
833 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); in gfx_v9_0_init_lbpw()
839 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); in gfx_v9_0_init_lbpw()
842 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF); in gfx_v9_0_init_lbpw()
[all …]
Dnbio_v6_1.c49 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v6_1_mc_access_enable()
53 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v6_1_mc_access_enable()
107 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, in nbio_v6_1_enable_doorbell_selfring_aperture()
109 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, in nbio_v6_1_enable_doorbell_selfring_aperture()
113 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); in nbio_v6_1_enable_doorbell_selfring_aperture()
128 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v6_1_ih_doorbell_range()
136 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v6_1_ih_control()
144 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v6_1_ih_control()
Dnbio_v7_0.c59 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v7_0_mc_access_enable()
62 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v7_0_mc_access_enable()
124 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v7_0_ih_doorbell_range()
131 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); in nbio_7_0_read_syshub_ind_mmr()
140 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); in nbio_7_0_write_syshub_ind_mmr()
141 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); in nbio_7_0_write_syshub_ind_mmr()
227 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v7_0_ih_control()
235 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v7_0_ih_control()
Ddf_v1_7.c44 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v1_7_enable_broadcast_mode()
46 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, in df_v1_7_enable_broadcast_mode()
82 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v1_7_update_medium_grain_clock_gating()
87 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v1_7_update_medium_grain_clock_gating()
Ddf_v3_6.c45 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v3_6_enable_broadcast_mode()
47 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, in df_v3_6_enable_broadcast_mode()
85 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v3_6_update_medium_grain_clock_gating()
90 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v3_6_update_medium_grain_clock_gating()
Dpsp_v3_1.c200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v3_1_bootloader_load_sysdrv()
203 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v3_1_bootloader_load_sysdrv()
260 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v3_1_bootloader_load_sos()
263 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v3_1_bootloader_load_sos()
335 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); in psp_v3_1_ring_create()
338 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); in psp_v3_1_ring_create()
341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); in psp_v3_1_ring_create()
345 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); in psp_v3_1_ring_create()
369 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); in psp_v3_1_ring_stop()
444 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); in psp_v3_1_cmd_submit()
[all …]
Dpsp_v10_0.c204 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); in psp_v10_0_ring_create()
207 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); in psp_v10_0_ring_create()
210 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); in psp_v10_0_ring_create()
214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); in psp_v10_0_ring_create()
238 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); in psp_v10_0_ring_stop()
311 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); in psp_v10_0_cmd_submit()
Dsoc15.c163 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); in soc15_gc_cac_rreg()
174 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); in soc15_gc_cac_wreg()
175 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); in soc15_gc_cac_wreg()
185 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); in soc15_se_cac_rreg()
196 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); in soc15_se_cac_wreg()
197 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); in soc15_se_cac_wreg()
Dsoc15_common.h41 #define WREG32_SOC15(ip, inst, reg, value) \ macro
Dgmc_v9_0.c1038 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); in gmc_v9_0_gart_enable()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/
Dsmu9_smumgr.c43 WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2, in smu9_is_smc_ram_running()
88 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu9_send_msg_to_smc_without_waiting()
106 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc()
132 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc_with_parameter()
134 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu9_send_msg_to_smc_with_parameter()
Dsmu10_smumgr.c66 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu10_send_msg_to_smc_without_waiting()
84 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu10_send_msg_to_smc()
102 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu10_send_msg_to_smc_with_parameter()
104 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu10_send_msg_to_smc_with_parameter()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_thermal.c141 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_fan_ctrl_set_static_mode()
144 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_fan_ctrl_set_static_mode()
161 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_fan_ctrl_set_default_mode()
165 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_fan_ctrl_set_default_mode()
277 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, in vega10_fan_ctrl_set_fan_speed_percent()
324 WREG32_SOC15(THM, 0, mmCG_TACH_STATUS, in vega10_fan_ctrl_set_fan_speed_rpm()
390 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); in vega10_thermal_set_temperature_range()
405 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, in vega10_thermal_initialize()
411 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_thermal_initialize()
445 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); in vega10_thermal_enable_alert()
[all …]
Dvega12_thermal.c196 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); in vega12_thermal_set_temperature_range()
215 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); in vega12_thermal_enable_alert()
228 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); in vega12_thermal_disable_alert()
Dvega10_powertune.c944 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_cac_driving_se_didt_config()
959 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_cac_driving_se_didt_config()
995 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_didt_config()
1004 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_didt_config()
1056 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_se_edc_config()
1067 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_config()
1106 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_edc_config()
1115 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_edc_config()
1165 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_force_stall_config()