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Searched refs:WREG32_NO_KIQ (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_ai.c141 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg()
143 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), in xgpu_ai_mailbox_trans_msg()
145 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg()
147 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), in xgpu_ai_mailbox_trans_msg()
230 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_ack_irq()
282 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_rcv_irq()
Dmxgpu_vi.c326 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_send_ack()
349 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_set_valid()
360 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg); in xgpu_vi_mailbox_trans_msg()
507 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_ack_irq()
536 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_rcv_irq()
Dsoc15_common.h45 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
Damdgpu_ttm.c1556 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); in amdgpu_ttm_access_memory()
1557 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); in amdgpu_ttm_access_memory()
1563 WREG32_NO_KIQ(mmMM_DATA, value); in amdgpu_ttm_access_memory()
2234 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); in amdgpu_ttm_vram_read()
2235 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); in amdgpu_ttm_vram_read()
2282 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); in amdgpu_ttm_vram_write()
2283 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); in amdgpu_ttm_vram_write()
2284 WREG32_NO_KIQ(mmMM_DATA, value); in amdgpu_ttm_vram_write()
Dvega10_ih.c217 WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); in vega10_ih_get_wptr()
Dgmc_v9_0.c341 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); in gmc_v9_0_flush_gpu_tlb()
Dvi.c115 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); in vi_smc_rreg()
Damdgpu.h1593 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) macro