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Searched refs:WREG32_FIELD (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dvce_v3_0.c166 WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0); in vce_v3_0_override_vce_clock_gating()
250 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_firmware_loaded()
252 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_firmware_loaded()
304 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1); in vce_v3_0_start()
309 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v3_0_start()
311 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_start()
317 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0); in vce_v3_0_start()
346 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0); in vce_v3_0_stop()
349 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_stop()
578 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v3_0_mc_resume()
[all …]
Dvce_v2_0.c201 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v2_0_mc_resume()
257 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v2_0_start()
258 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v2_0_start()
260 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v2_0_start()
515 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1); in vce_v2_0_soft_reset()
Dgfx_v8_0.c3862 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); in gfx_v8_0_gpu_init()
4078 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1); in gfx_v8_0_init_save_restore_list()
4117 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v8_0_enable_save_restore_machine()
4124 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60); in gfx_v8_0_init_power_gating()
4132 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3); in gfx_v8_0_init_power_gating()
4133 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); in gfx_v8_0_init_power_gating()
4140 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_up()
4146 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_down()
4151 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); in cz_enable_cp_power_gating()
4177 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
[all …]
Duvd_v6_0.c729 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); in uvd_v6_0_start()
732 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1); in uvd_v6_0_start()
748 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0); in uvd_v6_0_start()
783 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0); in uvd_v6_0_start()
803 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1); in uvd_v6_0_start()
805 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0); in uvd_v6_0_start()
850 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); in uvd_v6_0_start()
Dvce_v4_0.c709 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
714 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
719 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
901 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
920 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
Dgfx_v6_0.c2451 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
2520 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v6_0_rlc_reset()
2522 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()
2795 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); in gfx_v6_0_enable_gfx_cgpg()
2796 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); in gfx_v6_0_enable_gfx_cgpg()
2798 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); in gfx_v6_0_enable_gfx_cgpg()
2848 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); in gfx_v6_0_init_gfx_cgpg()
Duvd_v4_2.c616 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v4_2_set_dcm()
Damdgpu_amdkfd_gfx_v8.c580 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()
Damdgpu.h1656 #define WREG32_FIELD(reg, field, val) \ macro