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Searched refs:WDT (Results 1 – 25 of 47) sorted by relevance

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/Linux-v4.19/Documentation/devicetree/bindings/watchdog/
Dgpio-wdt.txt5 - gpios: From common gpio binding; gpio connection to WDT reset pin.
9 the WDT counter. The watchdog timer is disabled when GPIO is
11 - level: Low or high level starts counting WDT timeout,
12 the opposite level disables the WDT. Active level is determined
Dlpc18xx-wdt.txt1 * NXP LPC18xx Watchdog Timer (WDT)
5 - reg: Should contain WDT registers location and length
9 - interrupts: Should contain WDT interrupt
Dimgpdc-wdt.txt1 *ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT)
5 - reg : Should contain WDT registers location and length
9 - interrupts : Should contain WDT interrupt
Darm,sp805.txt3 SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
7 As SP805 WDT is a primecell IP, it follows the base bindings specified in
21 - interrupts: Should specify WDT interrupt number
22 - timeout-sec: Should specify default WDT timeout in seconds. If unset, the
Dfsl-imx-wdt.txt1 * Freescale i.MX Watchdog Timer (WDT) Controller
5 - reg : Should contain WDT registers location and length
6 - interrupts : Should contain WDT interrupt
Dsirfsoc_wdt.txt1 SiRFSoC Timer and Watchdog Timer(WDT) Controller
5 - reg: Address range of tick timer/WDT register set
Domap-wdt.txt1 TI Watchdog Timer (WDT) Controller for OMAP
5 - ti,hwmods : Name of the hwmod associated to the WDT
Drenesas-wdt.txt1 Renesas Watchdog Timer (WDT) Controller
28 - reg : Should contain WDT registers location and length
33 - power-domains : the power domain the WDT belongs to
Ddavinci-wdt.txt1 Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
5 - reg : Should contain WDT registers location and length
Dqca-ar7130-wdt.txt1 * Qualcomm Atheros AR7130 Watchdog Timer (WDT) Controller
Dingenic,jz4740-wdt.txt1 Ingenic Watchdog Timer (WDT) Controller for JZ4740 & JZ4780
/Linux-v4.19/arch/sh/kernel/cpu/sh4/
Dsetup-sh4-202.c91 HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT, enumerator
102 INTC_VECT(WDT, 0x560),
107 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
Dsetup-sh7750.c187 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, enumerator
203 INTC_VECT(WDT, 0x560),
209 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
Dsetup-sh7760.c39 WDT, REF, enumerator
76 INTC_VECT(WDT, 0x560),
107 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
/Linux-v4.19/arch/sh/kernel/cpu/sh3/
Dsetup-sh7710.c30 RTC, WDT, REF, enumerator
55 INTC_VECT(WDT, 0x560),
61 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
Dsetup-sh7705.c33 RTC, WDT, REF_RCMI, enumerator
53 INTC_VECT(WDT, 0x560),
59 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
Dsetup-sh770x.c34 RTC, WDT, REF, enumerator
44 INTC_VECT(WDT, 0x560),
71 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
Dsetup-sh7720.c226 WDT, REF_RCMI, SIM, enumerator
245 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
270 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
/Linux-v4.19/arch/sh/kernel/cpu/sh2/
Dsetup-sh7619.c24 WDT, EDMAC, CMT0, CMT1, enumerator
36 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
53 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
/Linux-v4.19/Documentation/watchdog/
Dwatchdog-parameters.txt14 wdt_stop: Acquire WDT 'stop' io port (default 0x43)
15 wdt_start: Acquire WDT 'start' io port (default 0x443)
20 wdt_stop: Advantech WDT 'stop' io port (default 0x443)
21 wdt_start: Advantech WDT 'start' io port (default 0x443)
90 io: Eurotech WDT io port (default=0x3f0)
91 irq: Eurotech WDT irq (default=10)
92 ev: Eurotech WDT event type (default is `int')
220 io: pc87413 WDT I/O port (default: io).
263 wdt_stop: SBC60xx WDT 'stop' io port (default 0x45)
264 wdt_start: SBC60xx WDT 'start' io port (default 0x443)
[all …]
Dwdt.txt3 WDT Watchdog Timer Interfaces For The Linux Operating System
46 The external event interfaces on the WDT boards are not currently supported.
/Linux-v4.19/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7763.c242 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
258 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
308 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
320 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
Dsetup-sh7780.c306 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
319 INTC_VECT(WDT, 0x560),
362 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
369 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
/Linux-v4.19/arch/sh/kernel/cpu/sh2a/
Dsetup-sh7206.c32 CMT0, CMT1, BSC, WDT, enumerator
63 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
114 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
/Linux-v4.19/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related

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