| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_0_init_cache_regs()
148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_0_init_cache_regs()
151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_0_init_cache_regs()
152 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_0_init_cache_regs()
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| D | mmhub_v1_0.c | 159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_0_init_cache_regs()
160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in mmhub_v1_0_init_cache_regs()
163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_0_init_cache_regs()
164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in mmhub_v1_0_init_cache_regs()
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| D | gmc_v7_0.c | 638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v7_0_gart_enable()
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v7_0_gart_enable()
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| D | gmc_v8_0.c | 844 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v8_0_gart_enable()
845 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
846 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v8_0_gart_enable()
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| D | sid.h | 387 #define VM_L2_CNTL3 0x502 macro
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| /Linux-v4.19/drivers/gpu/drm/radeon/ |
| D | rv770.c | 910 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
956 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
987 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
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| D | rv770d.h | 650 #define VM_L2_CNTL3 0x1408 macro
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| D | nid.h | 120 #define VM_L2_CNTL3 0x1408 macro
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| D | ni.c | 1298 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_enable()
1377 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_disable()
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| D | sid.h | 385 #define VM_L2_CNTL3 0x1408 macro
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| D | cikd.h | 503 #define VM_L2_CNTL3 0x1408 macro
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| D | r600.c | 1141 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_enable()
1193 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_disable()
1233 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_agp_enable()
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| D | evergreen.c | 2410 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2463 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2493 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
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| D | evergreend.h | 1158 #define VM_L2_CNTL3 0x1408 macro
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| D | r600d.h | 595 #define VM_L2_CNTL3 0x1408 macro
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| D | si.c | 4308 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_enable()
4394 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_disable()
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| D | cik.c | 5456 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5573 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()
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