Searched refs:VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER (Results 1 – 2 of 2) sorted by relevance
267 #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER 0x000000e5 /* 229 */ macro
375 …r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER… in dce_virtual_sw_init()
