Searched refs:VF610_CLK_PLL5_ENET (Results 1 – 2 of 2) sorted by relevance
40 #define VF610_CLK_PLL5_ENET 27 macro
251 clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet", "pll5_bypass", PLL5_CTRL, 13); in vf610_clocks_init()
