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Searched refs:UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c669 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
756 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v5_0_enable_mgcg()
765 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v5_0_enable_mgcg()
833 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) in uvd_v5_0_get_clockgating_state()
Duvd_v4_2.c596 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v4_2_enable_mgcg()
605 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v4_2_enable_mgcg()
620 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | in uvd_v4_2_set_dcm()
Duvd_v6_0.c1327 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
1417 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v6_0_enable_mgcg()
1426 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v6_0_enable_mgcg()
1499 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) in uvd_v6_0_get_clockgating_state()
Duvd_v7_0.c842 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); in uvd_v7_0_sriov_start()
955 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); in uvd_v7_0_start()
1595 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
Dvcn_v1_0.c355 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v1_0_disable_clock_gating()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h441 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro
Duvd_4_0_sh_mask.h36 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L macro
Duvd_4_2_sh_mask.h221 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro
Duvd_5_0_sh_mask.h241 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro
Duvd_6_0_sh_mask.h243 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h909 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro