Searched refs:UCR1_RRDYEN (Results 1 – 1 of 1) sorted by relevance
73 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro421 ucr1 |= UCR1_RRDYEN; in imx_uart_start_rx()476 ucr1 &= ~UCR1_RRDYEN; in imx_uart_stop_rx()878 if ((ucr1 & UCR1_RRDYEN) == 0) in imx_uart_int()1361 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()1409 ucr1 |= UCR1_RRDYEN; in imx_uart_startup()1473 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); in imx_uart_shutdown()1645 old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), in imx_uart_set_termios()1782 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN); in imx_uart_poll_init()1791 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()[all …]
