Searched refs:TILE_SPLIT (Results 1 – 15 of 15) sorted by relevance
79 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v6_0_tiling_mode_table_init()428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v6_0_tiling_mode_table_init()436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()448 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v6_0_tiling_mode_table_init()463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | in gfx_v6_0_tiling_mode_table_init()483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()[all …]
66 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro2246 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2250 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()2254 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v8_0_tiling_mode_table_init()2258 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v8_0_tiling_mode_table_init()2262 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2270 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2418 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2422 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()[all …]
1056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1060 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v7_0_tiling_mode_table_init()1064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v7_0_tiling_mode_table_init()1068 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v7_0_tiling_mode_table_init()1073 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1080 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1081 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1095 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1111 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1131 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()[all …]
193 # define TILE_SPLIT(x) ((x) << 11) macro
1129 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1196 # define TILE_SPLIT(x) ((x) << 11) macro
1879 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1902 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
1957 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2519 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2528 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2537 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in si_tiling_mode_table_init()2546 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2555 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2564 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2573 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2582 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2591 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()[all …]
2369 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2373 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2377 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2381 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); in cik_tiling_mode_table_init()2385 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2396 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2512 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2516 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2520 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()[all …]
1198 # define TILE_SPLIT(x) ((x) << 11) macro
1240 # define TILE_SPLIT(x) ((x) << 11) macro
2066 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in fill_plane_attributes_from_fb()