Searched refs:SYS_CLK_SPI0_MASTER (Results 1 – 3 of 3) sorted by relevance
158 #define SYS_CLK_SPI0_MASTER 7 macro
285 GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),
218 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
