1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
4 */
5
6 #ifndef _SUN8I_DW_HDMI_H_
7 #define _SUN8I_DW_HDMI_H_
8
9 #include <drm/bridge/dw_hdmi.h>
10 #include <drm/drm_encoder.h>
11 #include <linux/clk.h>
12 #include <linux/regmap.h>
13 #include <linux/reset.h>
14
15 #define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
16 #define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
17 #define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8)
18 #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8)
19 #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9)
20 #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16)
21 #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16)
22
23 #define SUN8I_HDMI_PHY_REXT_CTRL_REG 0x0004
24 #define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31)
25
26 #define SUN8I_HDMI_PHY_READ_EN_REG 0x0010
27 #define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545
28
29 #define SUN8I_HDMI_PHY_UNSCRAMBLE_REG 0x0014
30 #define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47
31
32 #define SUN8I_HDMI_PHY_ANA_CFG1_REG 0x0020
33 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI BIT(31)
34 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND BIT(30)
35 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC BIT(29)
36 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW BIT(28)
37 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVRCAL(x) ((x) << 26)
38 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(x) ((x) << 24)
39 #define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT BIT(23)
40 #define SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT BIT(22)
41 #define SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT BIT(21)
42 #define SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT BIT(20)
43 #define SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL BIT(19)
44 #define SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG BIT(18)
45 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS BIT(17)
46 #define SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN BIT(16)
47 #define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK GENMASK(15, 12)
48 #define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL (0xf << 12)
49 #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK BIT(11)
50 #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 BIT(10)
51 #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 BIT(9)
52 #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 BIT(8)
53 #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK BIT(7)
54 #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 BIT(6)
55 #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 BIT(5)
56 #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 BIT(4)
57 #define SUN8I_HDMI_PHY_ANA_CFG1_CKEN BIT(3)
58 #define SUN8I_HDMI_PHY_ANA_CFG1_LDOEN BIT(2)
59 #define SUN8I_HDMI_PHY_ANA_CFG1_ENVBS BIT(1)
60 #define SUN8I_HDMI_PHY_ANA_CFG1_ENBI BIT(0)
61
62 #define SUN8I_HDMI_PHY_ANA_CFG2_REG 0x0024
63 #define SUN8I_HDMI_PHY_ANA_CFG2_M_EN BIT(31)
64 #define SUN8I_HDMI_PHY_ANA_CFG2_PLLDBEN BIT(30)
65 #define SUN8I_HDMI_PHY_ANA_CFG2_SEN BIT(29)
66 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDPD BIT(28)
67 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDEN BIT(27)
68 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLRCK BIT(26)
69 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLR(x) ((x) << 23)
70 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK BIT(22)
71 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN BIT(21)
72 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_CD(x) ((x) << 19)
73 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(x) ((x) << 17)
74 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK BIT(16)
75 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW BIT(15)
76 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(x) ((x) << 13)
77 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(x) ((x) << 10)
78 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOSTCK(x) ((x) << 8)
79 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOST(x) ((x) << 6)
80 #define SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(x) ((x) << 0)
81
82 #define SUN8I_HDMI_PHY_ANA_CFG3_REG 0x0028
83 #define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOWCK(x) ((x) << 30)
84 #define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOW(x) ((x) << 28)
85 #define SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(x) ((x) << 18)
86 #define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(x) ((x) << 14)
87 #define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMPCK(x) ((x) << 11)
88 #define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(x) ((x) << 7)
89 #define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(x) ((x) << 4)
90 #define SUN8I_HDMI_PHY_ANA_CFG3_SDAPD BIT(3)
91 #define SUN8I_HDMI_PHY_ANA_CFG3_SDAEN BIT(2)
92 #define SUN8I_HDMI_PHY_ANA_CFG3_SCLPD BIT(1)
93 #define SUN8I_HDMI_PHY_ANA_CFG3_SCLEN BIT(0)
94
95 #define SUN8I_HDMI_PHY_PLL_CFG1_REG 0x002c
96 #define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 BIT(31)
97 #define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD BIT(30)
98 #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29)
99 #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28)
100 #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27)
101 #define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26)
102 #define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26
103 #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25)
104 #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22)
105 #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20)
106 #define SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN BIT(19)
107 #define SUN8I_HDMI_PHY_PLL_CFG1_CS BIT(18)
108 #define SUN8I_HDMI_PHY_PLL_CFG1_CP_S(x) ((x) << 13)
109 #define SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(x) ((x) << 7)
110 #define SUN8I_HDMI_PHY_PLL_CFG1_BWS BIT(6)
111 #define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK GENMASK(5, 0)
112 #define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT 0
113
114 #define SUN8I_HDMI_PHY_PLL_CFG2_REG 0x0030
115 #define SUN8I_HDMI_PHY_PLL_CFG2_SV_H BIT(31)
116 #define SUN8I_HDMI_PHY_PLL_CFG2_PDCLKSEL(x) ((x) << 29)
117 #define SUN8I_HDMI_PHY_PLL_CFG2_CLKSTEP(x) ((x) << 27)
118 #define SUN8I_HDMI_PHY_PLL_CFG2_PSET(x) ((x) << 24)
119 #define SUN8I_HDMI_PHY_PLL_CFG2_PCLK_SEL BIT(23)
120 #define SUN8I_HDMI_PHY_PLL_CFG2_AUTOSYNC_DIS BIT(22)
121 #define SUN8I_HDMI_PHY_PLL_CFG2_VREG2_OUT_EN BIT(21)
122 #define SUN8I_HDMI_PHY_PLL_CFG2_VREG1_OUT_EN BIT(20)
123 #define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN BIT(19)
124 #define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN(x) ((x) << 16)
125 #define SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(x) ((x) << 12)
126 #define SUN8I_HDMI_PHY_PLL_CFG2_VCO_RST_IN BIT(11)
127 #define SUN8I_HDMI_PHY_PLL_CFG2_SINT_FRAC BIT(10)
128 #define SUN8I_HDMI_PHY_PLL_CFG2_SDIV2 BIT(9)
129 #define SUN8I_HDMI_PHY_PLL_CFG2_S(x) ((x) << 6)
130 #define SUN8I_HDMI_PHY_PLL_CFG2_S6P25_7P5 BIT(5)
131 #define SUN8I_HDMI_PHY_PLL_CFG2_S5_7 BIT(4)
132 #define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK GENMASK(3, 0)
133 #define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT 0
134 #define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(x) (((x) - 1) << 0)
135
136 #define SUN8I_HDMI_PHY_PLL_CFG3_REG 0x0034
137 #define SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2 BIT(0)
138
139 #define SUN8I_HDMI_PHY_ANA_STS_REG 0x0038
140 #define SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT 11
141 #define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK GENMASK(16, 11)
142 #define SUN8I_HDMI_PHY_ANA_STS_RCALEND2D BIT(7)
143 #define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK GENMASK(5, 0)
144
145 #define SUN8I_HDMI_PHY_CEC_REG 0x003c
146
147 struct sun8i_hdmi_phy;
148
149 struct sun8i_hdmi_phy_variant {
150 bool has_phy_clk;
151 bool has_second_pll;
152 void (*phy_init)(struct sun8i_hdmi_phy *phy);
153 void (*phy_disable)(struct dw_hdmi *hdmi,
154 struct sun8i_hdmi_phy *phy);
155 int (*phy_config)(struct dw_hdmi *hdmi,
156 struct sun8i_hdmi_phy *phy,
157 unsigned int clk_rate);
158 };
159
160 struct sun8i_hdmi_phy {
161 struct clk *clk_bus;
162 struct clk *clk_mod;
163 struct clk *clk_phy;
164 struct clk *clk_pll0;
165 struct clk *clk_pll1;
166 unsigned int rcal;
167 struct regmap *regs;
168 struct reset_control *rst_phy;
169 struct sun8i_hdmi_phy_variant *variant;
170 };
171
172 struct sun8i_dw_hdmi {
173 struct clk *clk_tmds;
174 struct device *dev;
175 struct dw_hdmi *hdmi;
176 struct drm_encoder encoder;
177 struct sun8i_hdmi_phy *phy;
178 struct dw_hdmi_plat_data plat_data;
179 struct reset_control *rst_ctrl;
180 };
181
182 static inline struct sun8i_dw_hdmi *
encoder_to_sun8i_dw_hdmi(struct drm_encoder * encoder)183 encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
184 {
185 return container_of(encoder, struct sun8i_dw_hdmi, encoder);
186 }
187
188 int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node);
189 void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
190
191 void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
192 const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
193
194 int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
195 bool second_parent);
196
197 #endif /* _SUN8I_DW_HDMI_H_ */
198
