Searched refs:STMP_OFFSET_REG_SET (Results 1 – 10 of 10) sorted by relevance
112 ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_map_ts_channel()294 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_setup_touch_detection()316 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_prepare_x_pos()342 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_prepare_y_pos()368 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_prepare_pressure()385 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_enable_touch_detection()393 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_start_touch_event()461 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_finish_touch_event()581 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_ts_hw_init()
90 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_setup_transfer()310 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()316 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()326 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()329 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()338 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()373 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_transfer_one()410 STMP_OFFSET_REG_SET); in mxs_spi_transfer_one()
93 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); in stmp3xxx_wdt_set_timeout()95 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET); in stmp3xxx_wdt_set_timeout()199 STMP_OFFSET_REG_SET); in stmp3xxx_alarm_irq_enable()201 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); in stmp3xxx_alarm_irq_enable()353 STMP_OFFSET_REG_SET); in stmp3xxx_rtc_probe()
171 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()179 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()185 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()186 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()449 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; in mxs_lradc_adc_configure_trigger()519 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()520 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()522 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()
219 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_reset_chan()244 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); in mxs_dma_reset_chan()289 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_pause_chan()292 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); in mxs_dma_pause_chan()704 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_init()706 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_init()711 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); in mxs_dma_init()
15 #define STMP_OFFSET_REG_SET 0x4 macro
56 writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET); in stmp_reset_block()
86 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); in mxs_ocotp_read()
77 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET); in timrot_irq_enable()
536 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_mmc_enable_sdio_irq()538 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); in mxs_mmc_enable_sdio_irq()
