| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_hwseq.h | 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
44 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
45 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
46 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
47 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
48 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
52 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
53 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
54 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
55 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
[all …]
|
| D | dce_clock_source.h | 62 SRII(PHASE, DP_DTO, 0),\
63 SRII(PHASE, DP_DTO, 1),\
64 SRII(PHASE, DP_DTO, 2),\
65 SRII(PHASE, DP_DTO, 3),\
66 SRII(MODULO, DP_DTO, 0),\
67 SRII(MODULO, DP_DTO, 1),\
68 SRII(MODULO, DP_DTO, 2),\
69 SRII(MODULO, DP_DTO, 3),\
70 SRII(PIXEL_RATE_CNTL, OTG, 0), \
71 SRII(PIXEL_RATE_CNTL, OTG, 1), \
[all …]
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_mpc.h | 34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_BG_B_CB, MPCC, inst),\
43 SRII(MPCC_SM_CONTROL, MPCC, inst)
[all …]
|
| D | dcn10_resource.c | 176 #define SRII(reg_name, block, id)\ macro
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 436 #define SRII(reg_name, block, id)\ macro
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 623 #define SRII(reg_name, block, id)\ macro
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 450 #define SRII(reg_name, block, id)\ macro
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 456 #define SRII(reg_name, block, id)\ macro
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 500 #define SRII(reg_name, block, id)\ macro
|
