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Searched refs:SR (Results 1 – 25 of 102) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubbub.h33 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
34 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
35 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
37 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
38 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
39 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
40 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_dmcu.h33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
35 SR(DMCU_RAM_ACCESS_CTRL), \
36 SR(DMCU_IRAM_WR_CTRL), \
37 SR(DMCU_IRAM_WR_DATA), \
38 SR(MASTER_COMM_DATA_REG1), \
39 SR(MASTER_COMM_DATA_REG2), \
40 SR(MASTER_COMM_DATA_REG3), \
41 SR(MASTER_COMM_CMD_REG), \
42 SR(MASTER_COMM_CNTL_REG), \
[all …]
Ddce_hwseq.h31 SR(LVTMA_PWRSEQ_CNTL), \
32 SR(LVTMA_PWRSEQ_STATE)
49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
82 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
83 SR(DCFEV_CLOCK_CONTROL), \
92 SR(BLNDV_CONTROL),\
130 SR(DCHUB_FB_LOCATION),\
131 SR(DCHUB_AGP_BASE),\
132 SR(DCHUB_AGP_BOT),\
133 SR(DCHUB_AGP_TOP), \
[all …]
Ddce_abm.h33 SR(BL_PWM_PERIOD_CNTL), \
34 SR(BL_PWM_CNTL), \
35 SR(BL_PWM_CNTL2), \
36 SR(BL_PWM_GRP1_REG_LOCK), \
37 SR(LVTMA_PWRSEQ_REF_DIV), \
38 SR(MASTER_COMM_CNTL_REG), \
39 SR(MASTER_COMM_CMD_REG), \
40 SR(MASTER_COMM_DATA_REG1)
44 SR(DC_ABM1_HG_SAMPLE_RATE), \
45 SR(DC_ABM1_LS_SAMPLE_RATE), \
[all …]
Ddce_audio.h33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
36 SR(DCCG_AUDIO_DTO_SOURCE),\
37 SR(DCCG_AUDIO_DTO0_MODULE),\
38 SR(DCCG_AUDIO_DTO0_PHASE),\
39 SR(DCCG_AUDIO_DTO1_MODULE),\
40 SR(DCCG_AUDIO_DTO1_PHASE)
Ddce_link_encoder.h47 SR(DMCU_RAM_ACCESS_CTRL), \
48 SR(DMCU_IRAM_RD_CTRL), \
49 SR(DMCU_IRAM_RD_DATA), \
50 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
76 SR(DCI_MEM_PWR_STATUS)
86 SR(DCI_MEM_PWR_STATUS)
93 SR(DCI_MEM_PWR_STATUS)
99 SR(DCI_MEM_PWR_STATUS)
Ddce_aux.h37 SR(AUXN_IMPCAL), \
38 SR(AUXP_IMPCAL)
/Linux-v4.19/Documentation/networking/
Dseg6-sysctl.txt4 Accept or drop SR-enabled IPv6 packets on this interface.
12 Define HMAC policy for ingress SR-enabled packets on this interface.
15 0 - Accept SR packets without HMAC, validate SR packets with HMAC
16 1 - Drop SR packets without HMAC, validate SR packets with HMAC
Dixgbe.txt45 SR Modules
46 Intel DUAL RATE 1G/10G SFP+ SR (bailed) FTLX8571D3BCV-IT
47 Intel DUAL RATE 1G/10G SFP+ SR (bailed) AFBR-703SDDZ-IN1
48 Intel DUAL RATE 1G/10G SFP+ SR (bailed) AFBR-703SDZ-IN2
59 Finisar SFP+ SR bailed, 10g single rate FTLX8571D3BCL
60 Avago SFP+ SR bailed, 10g single rate AFBR-700SDZ
63 Finisar DUAL RATE 1G/10G SFP+ SR (No Bail) FTLX8571D3QCV-IT
64 Avago DUAL RATE 1G/10G SFP+ SR (No Bail) AFBR-703SDZ-IN1
83 their original module type (i.e., the Intel(R) 10 Gigabit SR Dual Port
84 Express Module only supports SR optical modules). If you plug in a different
[all …]
/Linux-v4.19/Documentation/PCI/
Dpci-iov-howto.txt11 1.1 What is SR-IOV
13 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
28 2.1 How can I enable SR-IOV capability
30 Multiple methods are available for SR-IOV enablement.
32 enabling and disabling of the capability via API provided by SR-IOV core.
33 If the hardware has SR-IOV capability, loading its PF driver would
54 3.1 SR-IOV API
56 To enable SR-IOV capability:
64 To disable SR-IOV capability:
72 command below before enabling SR-IOV capabilities. This is the
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/i2caux/dce110/
Di2c_hw_engine_dce110.h32 SR(DC_I2C_ARBITRATION),\
33 SR(DC_I2C_CONTROL),\
34 SR(DC_I2C_SW_STATUS),\
35 SR(DC_I2C_TRANSACTION0),\
36 SR(DC_I2C_TRANSACTION1),\
37 SR(DC_I2C_TRANSACTION2),\
38 SR(DC_I2C_TRANSACTION3),\
39 SR(DC_I2C_DATA),\
40 SR(MICROSECOND_TIME_BASE_DIV)
Daux_engine_dce110.h38 SR(AUXN_IMPCAL), \
39 SR(AUXP_IMPCAL)
/Linux-v4.19/drivers/macintosh/
Dvia-cuda.c47 #define SR (10*RS) /* Shift register */ macro
346 (void)in_8(&via[SR]); in sync_egret()
361 (void)in_8(&via[SR]); in sync_egret()
389 (void)in_8(&via[SR]); /* clear any left-over data */ in cuda_init_via()
398 (void)in_8(&via[SR]); in cuda_init_via()
409 (void)in_8(&via[SR]); in cuda_init_via()
418 (void)in_8(&via[SR]); in cuda_init_via()
546 out_8(&via[SR], current_req->data[data_index++]); in cuda_start()
598 (void)in_8(&via[SR]); in cuda_interrupt()
608 (void)in_8(&via[SR]); in cuda_interrupt()
[all …]
Dvia-macii.c53 #define SR (10*RS) /* Shift register */ macro
188 x = via[SR]; in macii_init_via()
363 via[SR] = req->data[1]; in macii_start()
415 x = via[SR]; in macii_interrupt()
457 x = via[SR]; in macii_interrupt()
462 via[SR] = req->data[data_index++]; in macii_interrupt()
475 x = via[SR]; in macii_interrupt()
516 x = via[SR]; in macii_interrupt()
/Linux-v4.19/arch/alpha/math-emu/
Dmath.c103 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in alpha_fp_emul()
137 FP_SUB_S(SR, SA, SB); in alpha_fp_emul()
141 FP_ADD_S(SR, SA, SB); in alpha_fp_emul()
145 FP_MUL_S(SR, SA, SB); in alpha_fp_emul()
149 FP_DIV_S(SR, SA, SB); in alpha_fp_emul()
153 FP_SQRT_S(SR, SB); in alpha_fp_emul()
223 FP_CONV(S,D,1,1,SR,DB); in alpha_fp_emul()
261 FP_FROM_INT_S(SR, ((long)vb), 64, long); in alpha_fp_emul()
273 FP_PACK_SP(&vc, SR); in alpha_fp_emul()
/Linux-v4.19/arch/sparc/math-emu/
Dmath_32.c286 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_one_mathemu()
428 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_one_mathemu()
432 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_one_mathemu()
436 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_one_mathemu()
444 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_one_mathemu()
448 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_one_mathemu()
460 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_one_mathemu()
467 case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; in do_one_mathemu()
468 case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; in do_one_mathemu()
507 case 5: FP_PACK_SP (rd, SR); break; in do_one_mathemu()
Dmath_64.c181 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_mathemu()
433 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_mathemu()
437 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_mathemu()
441 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_mathemu()
449 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_mathemu()
453 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_mathemu()
471 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; in do_mathemu()
474 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_mathemu()
481 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; in do_mathemu()
482 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; in do_mathemu()
[all …]
/Linux-v4.19/Documentation/sh/
Dregister-banks.txt8 bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
11 SR.RB banking
15 r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
17 when in the context of another bank. The developer must keep the SR.RB value
30 - The SR.IMASK interrupt handler makes use of this to set the
/Linux-v4.19/arch/sh/kernel/
Dhead_64.S160 getcon SR, r29
162 putcon r20, SR
249 getcon SR, r21
292 getcon SR, r21
295 putcon r22, SR /* Try to enable */
296 getcon SR, r22
/Linux-v4.19/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc.c293 #define SR(reg) \ macro
304 SR(IRQENABLE); in dispc_save_context()
305 SR(CONTROL); in dispc_save_context()
306 SR(CONFIG); in dispc_save_context()
307 SR(LINE_NUMBER); in dispc_save_context()
310 SR(GLOBAL_ALPHA); in dispc_save_context()
312 SR(CONTROL2); in dispc_save_context()
313 SR(CONFIG2); in dispc_save_context()
316 SR(CONTROL3); in dispc_save_context()
317 SR(CONFIG3); in dispc_save_context()
[all …]
/Linux-v4.19/drivers/gpu/drm/omapdrm/dss/
Ddispc.c437 #define SR(dispc, reg) \ macro
448 SR(dispc, IRQENABLE); in dispc_save_context()
449 SR(dispc, CONTROL); in dispc_save_context()
450 SR(dispc, CONFIG); in dispc_save_context()
451 SR(dispc, LINE_NUMBER); in dispc_save_context()
454 SR(dispc, GLOBAL_ALPHA); in dispc_save_context()
456 SR(dispc, CONTROL2); in dispc_save_context()
457 SR(dispc, CONFIG2); in dispc_save_context()
460 SR(dispc, CONTROL3); in dispc_save_context()
461 SR(dispc, CONFIG3); in dispc_save_context()
[all …]
/Linux-v4.19/drivers/media/pci/ngene/
Dngene-core.c92 while (Cur->ngeneBuffer.SR.Flags & 0x80) { in demux_tasklet()
95 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_tasklet()
101 Cur->ngeneBuffer.SR. in demux_tasklet()
115 Cur->ngeneBuffer.SR.Flags &= in demux_tasklet()
128 Cur->ngeneBuffer.SR.Flags &= ~0x40; in demux_tasklet()
135 Cur->ngeneBuffer.SR.DTOUpdate = in demux_tasklet()
144 if (Cur->ngeneBuffer.SR.Flags & 0x01) in demux_tasklet()
146 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_tasklet()
152 Cur->ngeneBuffer.SR.Clock, in demux_tasklet()
157 Cur->ngeneBuffer.SR.Clock, in demux_tasklet()
[all …]
/Linux-v4.19/arch/sh/include/cpu-sh5/cpu/
Dregisters.h25 #define SR cr0 macro
87 #define __SR __str(SR)
/Linux-v4.19/arch/sh/kernel/cpu/sh2a/
Dentry.S49 bld.b #6,@(0,r2) !previus SR.MD
50 bst.b #6,@(4*4,r15) !set cpu mode to SR.MD
53 bset.b #6,@(0,r2) !set SR.MD
66 mov.l r0,@-r15 ! original SR
94 mov.l @r8+,r11 ! old SR
/Linux-v4.19/drivers/staging/unisys/Documentation/ABI/
Dsysfs-platform-visorchipset59 responsible for enabling and disabling SR-IOV devices when the
62 Some SR-IOV devices have problems when the PF is reset without
78 responsible for enabling and disabling SR-IOV devices when the
81 Some SR-IOV devices have problems when the PF is reset without

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