Searched refs:SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (Results 1 – 2 of 2) sorted by relevance
71 #define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0 << 0) macro
455 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()478 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: in tegra_clk_sor_pad_get_parent()2299 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
