Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_1 (Results 1 – 2 of 2) sorted by relevance
47 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 macro
617 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers()620 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()629 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ss_dividers()632 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers()683 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_display_wm()686 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_display_wm()695 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_vce_wm()698 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_vce_wm()
