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Searched refs:SM (Results 1 – 25 of 46) sorted by relevance

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/Linux-v4.19/drivers/net/wireless/ath/ath9k/
Dar9003_aic.c181 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9003_aic_cal_start()
182 SM(127, AR_PHY_AIC_CAL_MAX_HOP_COUNT) | in ar9003_aic_cal_start()
183 SM(min_valid_count, AR_PHY_AIC_CAL_MIN_VALID_COUNT) | in ar9003_aic_cal_start()
184 SM(37, AR_PHY_AIC_F_WLAN) | in ar9003_aic_cal_start()
185 SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) | in ar9003_aic_cal_start()
186 SM(0, AR_PHY_AIC_CAL_ENABLE) | in ar9003_aic_cal_start()
187 SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | in ar9003_aic_cal_start()
188 SM(0, AR_PHY_AIC_ENABLE))); in ar9003_aic_cal_start()
191 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9003_aic_cal_start()
192 SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) | in ar9003_aic_cal_start()
[all …]
Dar9003_rtt.c77 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA); in ar9003_hw_rtt_load_hist_entry()
80 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_load_hist_entry()
81 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_load_hist_entry()
82 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_load_hist_entry()
86 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_load_hist_entry()
95 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE); in ar9003_hw_rtt_load_hist_entry()
146 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_fill_hist_entry()
147 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_fill_hist_entry()
148 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_fill_hist_entry()
153 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_fill_hist_entry()
Dbtcoex.c87 SM(ath_bt_config.wl_active_time, AR_BT_WL_ACTIVE_TIME) | in ath9k_hw_init_btcoex_hw()
88 SM(ath_bt_config.wl_qc_time, AR_BT_WL_QC_TIME); in ath9k_hw_init_btcoex_hw()
97 SM(time_extend, AR_BT_TIME_EXTEND) | in ath9k_hw_init_btcoex_hw()
98 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | in ath9k_hw_init_btcoex_hw()
99 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | in ath9k_hw_init_btcoex_hw()
100 SM(ath_bt_config.bt_mode, AR_BT_MODE) | in ath9k_hw_init_btcoex_hw()
101 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) | in ath9k_hw_init_btcoex_hw()
102 SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) | in ath9k_hw_init_btcoex_hw()
103 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) | in ath9k_hw_init_btcoex_hw()
104 SM(first_slot_time, AR_BT_FIRST_SLOT_TIME) | in ath9k_hw_init_btcoex_hw()
[all …]
Dar9003_mci.c868 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
869 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
870 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
871 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
872 SM(1, AR_BTCOEX_CTRL_NUM_ANTENNAS) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
873 SM(1, AR_BTCOEX_CTRL_RX_CHAIN_MASK) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
874 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
875 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
876 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
887 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | in ar9003_mci_set_btcoex_ctrl_9565_2ANT()
[all …]
Dar9002_phy.c239 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar9002_hw_spur_mitigate()
268 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar9002_hw_spur_mitigate()
269 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar9002_hw_spur_mitigate()
320 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
321 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
324 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
326 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
462 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); in ar9002_hw_set_bt_ant_diversity()
463 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9002_hw_set_bt_ant_diversity()
464 regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9002_hw_set_bt_ant_diversity()
[all …]
Deeprom_9287.c443 regval = SM(pdGainOverlap_t2, in ath9k_hw_set_ar9287_power_cal_table()
445 | SM(gainBoundaries[0], in ath9k_hw_set_ar9287_power_cal_table()
447 | SM(gainBoundaries[1], in ath9k_hw_set_ar9287_power_cal_table()
449 | SM(gainBoundaries[2], in ath9k_hw_set_ar9287_power_cal_table()
451 | SM(gainBoundaries[3], in ath9k_hw_set_ar9287_power_cal_table()
873 SM(pModal->iqCalICh[i], in ath9k_hw_ar9287_set_board_values()
875 SM(pModal->iqCalQCh[i], in ath9k_hw_ar9287_set_board_values()
906 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_ar9287_set_board_values()
907 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) in ath9k_hw_ar9287_set_board_values()
908 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) in ath9k_hw_ar9287_set_board_values()
[all …]
Dar9002_mac.c227 ctl6 = SM(i->keytype, AR_EncrType); in ar9002_set_txdesc()
243 | SM(0, AR_BurstDur)); in ar9002_set_txdesc()
261 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) in ar9002_set_txdesc()
262 | SM(i->type, AR_FrameType) in ar9002_set_txdesc()
269 ctl6 |= SM(i->aggr_len, AR_AggrLen); in ar9002_set_txdesc()
273 ctl6 |= SM(i->ndelim, AR_PadDelim); in ar9002_set_txdesc()
284 | SM(i->txpower[0], AR_XmitPower0) in ar9002_set_txdesc()
308 | SM(i->rtscts_rate, AR_RTSCTSRate)); in ar9002_set_txdesc()
310 WRITE_ONCE(ads->ds_ctl9, SM(i->txpower[1], AR_XmitPower1)); in ar9002_set_txdesc()
311 WRITE_ONCE(ads->ds_ctl10, SM(i->txpower[2], AR_XmitPower2)); in ar9002_set_txdesc()
[all …]
Dmac.c33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) in ath9k_hw_set_txq_interrupts()
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); in ath9k_hw_set_txq_interrupts()
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); in ath9k_hw_updatetxtriglevel()
391 SM(cwMin, AR_D_LCL_IFS_CWMIN) | in ath9k_hw_resettxqueue()
392 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | in ath9k_hw_resettxqueue()
393 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
396 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | in ath9k_hw_resettxqueue()
397 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | in ath9k_hw_resettxqueue()
[all …]
Dar5008_phy.c458 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar5008_hw_spur_mitigate()
468 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar5008_hw_spur_mitigate()
469 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar5008_hw_spur_mitigate()
902 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ar9160_hw_compute_pll_control()
905 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
907 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
910 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
912 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
925 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
927 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
[all …]
Dar9003_mac.c74 | SM(0, AR_BurstDur)); in ar9003_set_txdesc()
90 ctl17 = SM(i->keytype, AR_EncrType); in ar9003_set_txdesc()
104 | SM(i->txpower[0], AR_XmitPower0) in ar9003_set_txdesc()
113 SM(i->keyix, AR_DestIdx) : 0) in ar9003_set_txdesc()
114 | SM(i->type, AR_FrameType) in ar9003_set_txdesc()
122 ctl17 |= SM(i->aggr_len, AR_AggrLen); in ar9003_set_txdesc()
126 ctl17 |= SM(i->ndelim, AR_PadDelim); in ar9003_set_txdesc()
136 ctl12 |= SM(val, AR_PAPRDChainMask); in ar9003_set_txdesc()
151 | SM(i->rtscts_rate, AR_RTSCTSRate)); in ar9003_set_txdesc()
155 WRITE_ONCE(ads->ctl20, SM(i->txpower[1], AR_XmitPower1)); in ar9003_set_txdesc()
[all …]
Deeprom_4k.c347 SM(pdGainOverlap_t2, in ath9k_hw_set_4k_power_cal_table()
349 | SM(gainBoundaries[0], in ath9k_hw_set_4k_power_cal_table()
351 | SM(gainBoundaries[1], in ath9k_hw_set_4k_power_cal_table()
353 | SM(gainBoundaries[2], in ath9k_hw_set_4k_power_cal_table()
355 | SM(gainBoundaries[3], in ath9k_hw_set_4k_power_cal_table()
708 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | in ath9k_hw_4k_set_gain()
709 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF), in ath9k_hw_4k_set_gain()
784 regVal |= SM(ant_div_control1, in ath9k_hw_4k_set_board_values()
786 regVal |= SM(ant_div_control2, in ath9k_hw_4k_set_board_values()
788 regVal |= SM((ant_div_control2 >> 2), in ath9k_hw_4k_set_board_values()
[all …]
Deeprom_def.c440 SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN), in ath9k_hw_def_set_gain()
443 SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN), in ath9k_hw_def_set_gain()
457 SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN), in ath9k_hw_def_set_gain()
460 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN), in ath9k_hw_def_set_gain()
499 SM(pModal->iqCalICh[i], in ath9k_hw_def_set_board_values()
501 SM(pModal->iqCalQCh[i], in ath9k_hw_def_set_board_values()
568 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_def_set_board_values()
569 | SM(pModal->txEndToXpaOff, in ath9k_hw_def_set_board_values()
571 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
573 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
[all …]
Dar9003_phy.c608 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); in ar9003_hw_compute_pll_control_soc()
611 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
613 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
615 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); in ar9003_hw_compute_pll_control_soc()
625 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); in ar9003_hw_compute_pll_control()
628 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
630 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
632 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); in ar9003_hw_compute_pll_control()
1483 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_set_radar_params()
1484 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); in ar9003_hw_set_radar_params()
[all …]
Dmac.h22 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
25 (SM((_series)[_index].Rate, AR_XmitRate##_index))
28 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
39 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
/Linux-v4.19/drivers/iio/chemical/
DKconfig8 tristate "Atlas Scientific OEM SM sensors"
16 Atlas Scientific OEM SM sensors:
17 * pH SM sensor
18 * EC SM sensor
19 * ORP SM sensor
/Linux-v4.19/drivers/net/wireless/ath/ath6kl/
Dhif.c213 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
216 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
577 SM(INT_STATUS_ENABLE_ERROR, 0x01) | in ath6kl_hif_enable_intrs()
578 SM(INT_STATUS_ENABLE_CPU, 0x01) | in ath6kl_hif_enable_intrs()
579 SM(INT_STATUS_ENABLE_COUNTER, 0x01); in ath6kl_hif_enable_intrs()
585 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_enable_intrs()
592 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | in ath6kl_hif_enable_intrs()
593 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); in ath6kl_hif_enable_intrs()
599 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, in ath6kl_hif_enable_intrs()
/Linux-v4.19/drivers/net/wireless/ath/ath10k/
Dhw.c679 slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT); in ath10k_hw_qca988x_set_coverage_class()
686 ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); in ath10k_hw_qca988x_set_coverage_class()
692 cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); in ath10k_hw_qca988x_set_coverage_class()
782 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | in ath10k_hw_qca6174_enable_pll_clock()
783 SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV)); in ath10k_hw_qca6174_enable_pll_clock()
795 reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME); in ath10k_hw_qca6174_enable_pll_clock()
807 reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV); in ath10k_hw_qca6174_enable_pll_clock()
825 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
826 SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) | in ath10k_hw_qca6174_enable_pll_clock()
827 SM(1, WLAN_PLL_CONTROL_NOPWD)); in ath10k_hw_qca6174_enable_pll_clock()
[all …]
Dhtt_tx.c44 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | in ath10k_htt_tx_txq_calc_size()
45 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); in ath10k_htt_tx_txq_calc_size()
661 info |= SM(htt->tx_q_state.type, in ath10k_htt_send_frag_desc_bank_cfg_32()
723 info |= SM(htt->tx_q_state.type, in ath10k_htt_send_frag_desc_bank_cfg_64()
1227 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); in ath10k_htt_tx_32()
1230 flags0 |= SM(ATH10K_HW_TXRX_MGMT, in ath10k_htt_tx_32()
1264 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); in ath10k_htt_tx_32()
1265 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); in ath10k_htt_tx_32()
1429 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); in ath10k_htt_tx_64()
1432 flags0 |= SM(ATH10K_HW_TXRX_MGMT, in ath10k_htt_tx_64()
[all …]
Dpci.c2935 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, in ath10k_pci_enable_eeprom()
2937 SM(1, GPIO_PIN0_PAD_PULL)); in ath10k_pci_enable_eeprom()
2942 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | in ath10k_pci_enable_eeprom()
2943 SM(1, GPIO_PIN0_PAD_PULL)); in ath10k_pci_enable_eeprom()
2953 SM(1, SI_CONFIG_ERR_INT) | in ath10k_pci_enable_eeprom()
2954 SM(1, SI_CONFIG_BIDIR_OD_DATA) | in ath10k_pci_enable_eeprom()
2955 SM(1, SI_CONFIG_I2C) | in ath10k_pci_enable_eeprom()
2956 SM(1, SI_CONFIG_POS_SAMPLE) | in ath10k_pci_enable_eeprom()
2957 SM(1, SI_CONFIG_INACTIVE_DATA) | in ath10k_pci_enable_eeprom()
2958 SM(1, SI_CONFIG_INACTIVE_CLK) | in ath10k_pci_enable_eeprom()
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/display/
Dsm501fb.txt1 * SM SM501
3 The SM SM501 is a LCD controller, with proper hardware, it can also
/Linux-v4.19/arch/m68k/fpsp040/
Ddecbin.S31 | adds and muls in FP0. Set the sign according to SM.
40 | added if SM = 1 and subtracted if SM = 0. Scale the
43 | SM = 0 a non-zero digit in the integer position
44 | SM = 1 a non-zero digit in Mant0, lsd of the fraction
435 bfextu %d4{#0:#2},%d0 | {FPCR[6],FPCR[5],SM,SE}
/Linux-v4.19/Documentation/devicetree/bindings/iio/chemical/
Datlas,ec-sm.txt1 * Atlas Scientific EC-SM OEM sensor
Datlas,orp-sm.txt1 * Atlas Scientific ORP-SM OEM sensor
Datlas,ph-sm.txt1 * Atlas Scientific pH-SM OEM sensor
/Linux-v4.19/Documentation/filesystems/nfs/
Dnfs-rdma.txt175 If you are using InfiniBand, make sure there is a Subnet Manager (SM)
176 running on the network. If your IB switch has an embedded SM, you can
177 use it. Otherwise, you will need to run an SM, such as OpenSM, on one
180 If an SM is running on your network, you should see the following:

12