Searched refs:SIMD (Results 1 – 8 of 8) sorted by relevance
84 uint32_t SIMD:2; /* SIMD id */ member
507 reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD; in dbgdev_wave_control_set_registers()
349 Common glue for SIMD optimizations of the MORUS-640 dedicated AEAD372 Common glue for SIMD optimizations of the MORUS-1280 dedicated AEAD675 in IETF protocols. This is the x86_64 assembler implementation using SIMD849 using powerpc SPE SIMD instruction set.860 multiple data lanes concurrently with SIMD instructions for876 multiple data lanes concurrently with SIMD instructions for892 multiple data lanes concurrently with SIMD instructions for918 implemented using powerpc SPE SIMD instruction set.1462 This is the x86_64 assembler implementation using SIMD instructions.
448 * All SVE register bits that are not shared with FP/SIMD are caller-save.456 Appendix B. ARMv8-A FP/SIMD programmer's model464 ARMv8-A defines the following floating-point / SIMD register state:
2431 bool "Support for the MIPS SIMD Architecture"2435 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers2436 and a set of SIMD instructions to operate on them. When this option
2155 bool "Advanced SIMD (NEON) Extension support"2158 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1143 execution state which complements and extends the SIMD functionality
2034 arm64 core/FP-SIMD registers have the following id bit patterns. Note2078 if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector4234 This capability allows the use of the MIPS SIMD Architecture (MSA) by the guest.
