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Searched refs:SDMA0_CNTL (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dsdma_v3_0.c583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
1408 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1413 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1424 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1429 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
Dsdma_v2_4.c1072 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1077 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1088 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1093 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
Dsdma_v4_0.c568 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable()
695 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v4_0_gfx_resume()
1382 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
Dcik_sdma.c375 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
384 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
/Linux-v4.19/drivers/gpu/drm/radeon/
Dcik_reg.h204 #define SDMA0_CNTL 0xD010 macro
Dcik_sdma.c314 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
319 WREG32(SDMA0_CNTL + reg_offset, value); in cik_sdma_ctx_switch_enable()
Dcik.c6874 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6875 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6876 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6877 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
7059 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7060 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7230 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set()
7231 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
Dcikd.h1960 #define SDMA0_CNTL 0xD010 macro