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Searched refs:SCLK_PWM (Results 1 – 10 of 10) sorted by relevance

/Linux-v4.19/include/dt-bindings/clock/
Dexynos7-clk.h91 #define SCLK_PWM 11 macro
Ds5pv210.h194 #define SCLK_PWM 169 macro
Drv1108-cru.h80 #define SCLK_PWM 121 macro
Drk3328-cru.h58 #define SCLK_PWM 60 macro
/Linux-v4.19/arch/arm/boot/dts/
Drv1108.dtsi212 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
224 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
236 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
248 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
/Linux-v4.19/arch/arm64/boot/dts/rockchip/
Drk3328.dtsi401 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
412 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
423 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
435 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
/Linux-v4.19/drivers/clk/samsung/
Dclk-s5pv210.c633 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
Dclk-exynos7.c674 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
/Linux-v4.19/drivers/clk/rockchip/
Dclk-rk3328.c472 COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
Dclk-rv1108.c635 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,