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Searched refs:SCLK (Results 1 – 16 of 16) sorted by relevance

/Linux-v4.19/drivers/spi/
Dspi-lm70llp.c75 #define SCLK 0x40 macro
125 parport_write_data(pp->port, data | SCLK); in clkHigh()
132 parport_write_data(pp->port, data & ~SCLK); in clkLow()
/Linux-v4.19/Documentation/devicetree/bindings/sound/
Dpcm512x.txt19 - clocks : A clock specifier for the clock connected as SCLK. If this
27 external connection from the pll-out pin to the SCLK pin is assumed.
Dcs35l34.txt45 SCLK. Otherwise, data is on the falling edge of SCLK.
/Linux-v4.19/include/dt-bindings/clock/
Dmicrochip,pic32-clock.h26 #define SCLK 7 macro
/Linux-v4.19/Documentation/devicetree/bindings/spi/
Dspi_oc_tiny.txt9 the input clock to SCLK.
Dspi-rockchip.txt33 - rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
/Linux-v4.19/Documentation/devicetree/bindings/i2c/
Di2c-emev2.txt7 - clocks : phandle to the IP core SCLK
/Linux-v4.19/Documentation/hwmon/
Dlm7030 the driver accesses the LM70 using SPI communication: 16 SCLK cycles
/Linux-v4.19/drivers/clk/microchip/
Dclk-pic32mzda.c217 clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core); in pic32mzda_clk_probe()
/Linux-v4.19/Documentation/spi/
Dspi-lm70llp41 D6 8 --> SCLK 3
Dspi-summary181 physical SPI bus segment, with SCLK, MOSI, and MISO.
/Linux-v4.19/arch/arm/boot/dts/
Darmada-385-turris-omnia.dts344 /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
/Linux-v4.19/Documentation/input/devices/
Damijoy.rst102 the rising edge of SCLK. MLD output is used to parallel load
/Linux-v4.19/drivers/scsi/sym53c8xx_2/
Dsym_defs.h281 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
Dsym_hipd.c459 OUTB(np, nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
/Linux-v4.19/drivers/scsi/
Dncr53c8xx.h803 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro