Searched refs:RREG8 (Results 1 – 11 of 11) sorted by relevance
97 status = RREG8(MGAREG_Status + 2); in mga_wait_busy()307 tmp = RREG8(MGAREG_CRTC_DATA); in mga_g200wb_set_plls()314 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()319 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()324 tmp = RREG8(MGAREG_MEM_MISC_READ); in mga_g200wb_set_plls()329 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()337 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()352 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()360 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()366 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()[all …]
38 return RREG8(DAC_DATA); in mga_i2c_read_gpio()46 tmp = (RREG8(DAC_DATA) & mask) | val; in mga_i2c_set_gpio()
45 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) macro55 RREG8(0x1fda); \
39 #define RREG8(reg) ioread8(((void __iomem *)cdev->rmmio) + (reg)) macro80 RREG8(VGA_DAC_MASK); \81 RREG8(VGA_DAC_MASK); \82 RREG8(VGA_DAC_MASK); \83 RREG8(VGA_DAC_MASK); \
67 sr01 |= RREG8(SEQ_DATA) & ~0x20; in cirrus_crtc_dpms()71 gr0e |= RREG8(GFX_DATA) & ~0x06; in cirrus_crtc_dpms()86 tmp = RREG8(CRT_DATA); in cirrus_set_start_address()92 tmp = RREG8(CRT_DATA); in cirrus_set_start_address()233 sr07 = RREG8(SEQ_DATA); in cirrus_crtc_mode_set()
76 return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; in xgpu_ai_peek_ack()85 reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE); in xgpu_ai_poll_ack()
1595 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) macro
291 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) in radeon_wait_pll_lock()
3774 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()3827 tmp = RREG8(R_0003C2_GENMO_WT); in r100_vga_render_disable()
2516 #define RREG8(reg) readb((rdev->rmmio) + (reg)) macro
1146 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()
