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Searched refs:RREG32_SOC15 (Results 1 – 21 of 21) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dmmhub_v1_0.c40 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
110 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
121 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
142 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_init_cache_regs()
153 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
178 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
389 pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC); in mmhub_v1_0_initialize_power_gating()
390 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); in mmhub_v1_0_initialize_power_gating()
409 pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC); in mmhub_v1_0_initialize_power_gating()
410 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); in mmhub_v1_0_initialize_power_gating()
[all …]
Ddf_v1_7.c42 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
54 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
79 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
84 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
100 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
Ddf_v3_6.c43 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v3_6_enable_broadcast_mode()
55 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); in df_v3_6_get_fb_channel_number()
82 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v3_6_update_medium_grain_clock_gating()
87 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v3_6_update_medium_grain_clock_gating()
103 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v3_6_get_clockgating_state()
Dnbio_v7_0.c43 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v7_0_get_rev_id()
46 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_VG20); in nbio_v7_0_get_rev_id()
48 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v7_0_get_rev_id()
77 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); in nbio_v7_0_get_memsize()
116 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); in nbio_v7_0_ih_doorbell_range()
132 data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA); in nbio_7_0_read_syshub_ind_mmr()
228 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v7_0_ih_control()
Dvcn_v1_0.c218 if (RREG32_SOC15(VCN, 0, mmUVD_STATUS)) in vcn_v1_0_hw_fini()
335 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
346 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_disable_clock_gating()
351 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
361 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
384 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
408 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
435 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
462 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
471 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_enable_clock_gating()
[all …]
Dnbio_v6_1.c38 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v6_1_get_rev_id()
70 return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); in nbio_v6_1_get_memsize()
120 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); in nbio_v6_1_ih_doorbell_range()
137 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v6_1_ih_control()
250 reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER); in nbio_v6_1_detect_hw_virt()
Dgfxhub_v1_0.c35 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; in gfxhub_v1_0_get_mc_fb_offset()
108 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
129 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); in gfxhub_v1_0_init_cache_regs()
140 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); in gfxhub_v1_0_init_cache_regs()
167 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); in gfxhub_v1_0_enable_system_domain()
289 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_gart_disable()
312 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v1_0_set_fault_enable_default()
Dgfx_v9_0.c836 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); in gfx_v9_0_init_lbpw()
1096 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); in wave_read_ind()
1111 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); in wave_read_regs()
1199 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
1316 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); in gfx_v9_0_ngg_init()
1317 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); in gfx_v9_0_ngg_init()
1696 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); in gfx_v9_0_get_rb_active_bitmap()
1697 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); in gfx_v9_0_get_rb_active_bitmap()
1775 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); in gfx_v9_0_gpu_init()
1835 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v9_0_wait_for_rlc_serdes()
[all …]
Duvd_v7_0.c75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); in uvd_v7_0_ring_get_rptr()
90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in uvd_v7_0_enc_ring_get_rptr()
92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); in uvd_v7_0_enc_ring_get_rptr()
106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); in uvd_v7_0_ring_get_wptr()
124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); in uvd_v7_0_enc_ring_get_wptr()
126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); in uvd_v7_0_enc_ring_get_wptr()
386 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); in uvd_v7_0_early_init()
725 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); in uvd_v7_0_mmsch_start()
747 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); in uvd_v7_0_mmsch_start()
751 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); in uvd_v7_0_mmsch_start()
[all …]
Dpsp_v3_1.c184 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in psp_v3_1_bootloader_load_sysdrv()
244 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in psp_v3_1_bootloader_load_sos()
269 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v3_1_bootloader_load_sos()
272 ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); in psp_v3_1_bootloader_load_sos()
415 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v3_1_cmd_submit()
578 reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); in psp_v3_1_smu_reload_quirk()
Dvega10_ih.c47 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_enable_interrupts()
64 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_disable_interrupts()
100 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_irq_init()
138 ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega10_ih_irq_init()
152 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); in vega10_ih_irq_init()
157 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); in vega10_ih_irq_init()
Dsoc15_common.h35 #define RREG32_SOC15(ip, inst, reg) \ macro
Dgmc_v9_0.c801 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); in gmc_v9_0_get_vbios_fb_size()
819 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); in gmc_v9_0_get_vbios_fb_size()
829 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); in gmc_v9_0_get_vbios_fb_size()
1037 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); in gmc_v9_0_gart_enable()
Dpsp_v10_0.c284 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v10_0_cmd_submit()
Dsoc15.c164 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); in soc15_gc_cac_rreg()
186 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); in soc15_se_cac_rreg()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_thermal.c105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
142 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
145 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
267 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_percent()
278 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega10_fan_ctrl_set_fan_speed_percent()
325 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_set_fan_speed_rpm()
[all …]
Dvega12_thermal.c151 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); in vega12_thermal_get_temperature()
188 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega12_thermal_set_temperature_range()
Dsmu10_hwmgr.c291 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS); in smu10_is_gfx_on()
1066 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); in smu10_thermal_get_temperature()
Dvega10_hwmgr.c903 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & in vega10_hwmgr_backend_init()
3710 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & in vega10_read_sensor()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/
Dsmu9_smumgr.c46 mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2); in smu9_is_smc_ram_running()
74 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
149 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu9_get_argument()
Dsmu10_smumgr.c58 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
75 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu10_read_arg_from_smc()