Searched refs:RREG32_PCIE (Results 1 – 15 of 15) sorted by relevance
1398 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()1439 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()1446 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); in cik_pcie_gen3_enable()1471 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1475 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1503 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1526 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()1531 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()1554 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()1561 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in cik_program_aspm()[all …]
152 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_update_medium_grain_clock_gating()180 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_update_medium_grain_light_sleep()201 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_get_clockgating_state()206 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_get_clockgating_state()267 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); in nbio_v6_1_init_registers()
153 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); in nbio_v7_0_update_medium_grain_clock_gating()191 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_update_medium_grain_light_sleep()212 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_0_get_clockgating_state()217 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_get_clockgating_state()
1619 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()1772 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()1935 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()1943 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
65 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
1275 temp = data = RREG32_PCIE(ixPCIE_CNTL2); in vi_update_bif_medium_grain_light_sleep()1538 data = RREG32_PCIE(ixPCIE_CNTL2); in vi_common_get_clockgating_state()
242 value = RREG32_PCIE(*pos >> 2); in amdgpu_debugfs_regs_pcie_read()
854 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in gmc_v7_0_enable_bif_mgls()
1605 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) macro
4966 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) & in ci_get_current_pcie_speed()4977 link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) & in ci_get_current_pcie_lane_number()
89 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()91 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()175 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()195 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()533 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()549 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()551 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()567 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_get_pcie_lanes()594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info()596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info()[all …]
5568 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()7152 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()7267 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()7430 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()7438 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
131 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv6xx_enable_pll_sleep_in_l1()
122 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv770_enable_pll_sleep_in_l1()
2532 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) macro
