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Searched refs:REG_WAIT (Results 1 – 14 of 14) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_dmcu.c76 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_dmcu_load_iram()
100 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_get_dmcu_psr_state()
124 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_set_psr_enable()
221 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_setup_psr()
298 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); in dce_psr_wait_loop()
330 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_state()
357 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_version()
376 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_get_dmcu_version()
386 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_get_dmcu_version()
416 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
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Ddce_abm.c190 REG_WAIT(BL_PWM_GRP1_REG_LOCK, in driver_set_backlight_level()
219 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
299 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_level()
317 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_immediate_disable()
Ddce_aux.c120 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, in acquire_engine()
131 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, in acquire_engine()
245 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, in submit_channel_request()
371 value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, in get_channel_status()
Ddce_mem_input.c597 REG_WAIT(DMIF_BUFFER_CONTROL, in dce_mi_allocate_dmif()
634 REG_WAIT(DMIF_BUFFER_CONTROL, in dce_mi_free_dmif()
Ddce_stream_encoder.c89 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in dce110_update_generic_info_packet()
700 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, in dce110_stream_encoder_set_mst_bandwidth()
920 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in dce110_stream_encoder_dp_blank()
Ddce_opp.c498 REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10); in program_formatter_reset_dig_resync_fifo()
Ddce_transform.c201 REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10); in program_multi_taps_filter()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/i2caux/dce110/
Daux_engine_dce110.c150 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, in acquire_engine()
161 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, in acquire_engine()
273 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, in submit_channel_request()
399 value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, in get_channel_status()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_optc.c443 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, in optc1_enable_optc_clock()
451 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
511 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_disable_crtc()
626 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc1_lock()
780 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
786 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
Ddcn10_stream_encoder.c79 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_update_generic_info_packet()
630 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, in enc1_stream_encoder_set_mst_bandwidth()
802 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in enc1_stream_encoder_dp_blank()
Ddcn10_hw_sequencer.c426 REG_WAIT(DOMAIN1_PG_STATUS, in dpp_pg_control()
434 REG_WAIT(DOMAIN3_PG_STATUS, in dpp_pg_control()
442 REG_WAIT(DOMAIN5_PG_STATUS, in dpp_pg_control()
450 REG_WAIT(DOMAIN7_PG_STATUS, in dpp_pg_control()
478 REG_WAIT(DOMAIN0_PG_STATUS, in hubp_pg_control()
486 REG_WAIT(DOMAIN2_PG_STATUS, in hubp_pg_control()
494 REG_WAIT(DOMAIN4_PG_STATUS, in hubp_pg_control()
502 REG_WAIT(DOMAIN6_PG_STATUS, in hubp_pg_control()
Ddcn10_mpc.c101 REG_WAIT(MPCC_STATUS[id], in mpc1_assert_idle_mpcc()
Ddcn10_hubp.c60 REG_WAIT(DCHUBP_CNTL, in hubp1_set_blank()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h218 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \ macro