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Searched refs:REG_UPDATE_2 (Results 1 – 24 of 24) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_opp.c77 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
81 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
88 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
192 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
198 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
203 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
208 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
214 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
234 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in opp1_set_dyn_expansion()
246 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in opp1_set_dyn_expansion()
[all …]
Ddcn10_optc.c207 REG_UPDATE_2(OTG_H_SYNC_A, in optc1_program_timing()
229 REG_UPDATE_2(OTG_H_BLANK_START_END, in optc1_program_timing()
264 REG_UPDATE_2(OTG_V_SYNC_A, in optc1_program_timing()
284 REG_UPDATE_2(OTG_V_BLANK_START_END, in optc1_program_timing()
334 REG_UPDATE_2(CONTROL, in optc1_program_timing()
339 REG_UPDATE_2(OTG_CONTROL, in optc1_program_timing()
391 REG_UPDATE_2(OTG_BLANK_CONTROL, in optc1_unblank_crtc()
405 REG_UPDATE_2(OTG_BLANK_CONTROL, in optc1_blank_crtc()
439 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, in optc1_enable_optc_clock()
448 REG_UPDATE_2(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
[all …]
Ddcn10_stream_encoder.c333 REG_UPDATE_2(DP_PIXEL_FORMAT, in enc1_stream_encoder_dp_set_stream_attribute()
515 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
519 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
526 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
530 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
536 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
549 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
561 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
1196 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, in enc1_se_setup_hdmi_audio()
1244 REG_UPDATE_2(AFMT_60958_0, in enc1_se_setup_hdmi_audio()
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Ddcn10_hubp.c46 REG_UPDATE_2(DCHUBP_CNTL, in hubp1_set_blank()
187 REG_UPDATE_2(DCSURF_SURFACE_PITCH, in hubp1_program_size()
191 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, in hubp1_program_size()
211 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
215 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
245 REG_UPDATE_2(HUBPRET_CONTROL, in hubp1_program_pixel_format()
337 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, in hubp1_program_surface_flip_and_addr()
1049 REG_UPDATE_2(CURSOR_SIZE, in hubp1_cursor_set_attributes()
Ddcn10_link_encoder.c264 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, in set_dp_phy_pattern_symbol_error()
284 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, in set_dp_phy_pattern_prbs7()
484 REG_UPDATE_2(DP_SEC_CNTL1, in dcn10_psr_program_secondary_packet()
1186 REG_UPDATE_2(DP_MSE_SAT0, in dcn10_link_encoder_update_mst_stream_allocation_table()
1200 REG_UPDATE_2(DP_MSE_SAT0, in dcn10_link_encoder_update_mst_stream_allocation_table()
1214 REG_UPDATE_2(DP_MSE_SAT1, in dcn10_link_encoder_update_mst_stream_allocation_table()
1228 REG_UPDATE_2(DP_MSE_SAT1, in dcn10_link_encoder_update_mst_stream_allocation_table()
Ddcn10_hubbub.c113 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, in hubbub1_verify_allow_pstate_change_high()
166 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, in hubbub1_verify_allow_pstate_change_high()
471 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, in hubbub1_program_watermarks()
476 REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, in hubbub1_program_watermarks()
Ddcn10_dpp.c427 REG_UPDATE_2(CURSOR0_CONTROL, in dpp1_set_cursor_attributes()
483 REG_UPDATE_2(DPP_CONTROL, in dpp1_dppclk_control()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_opp.c188 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
192 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
198 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
272 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
391 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding()
396 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding()
457 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in dce110_opp_set_dyn_expansion()
468 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in dce110_opp_set_dyn_expansion()
473 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in dce110_opp_set_dyn_expansion()
478 REG_UPDATE_2( in dce110_opp_set_dyn_expansion()
Ddce_stream_encoder.c134 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
439 REG_UPDATE_2( in dce110_stream_encoder_dp_set_stream_attribute()
581 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
585 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
592 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
596 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
602 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
616 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
628 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
732 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, in dce110_stream_encoder_update_hdmi_info_packets()
[all …]
Ddce_abm.c178 REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK, in driver_set_backlight_level()
211 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dmcu_set_backlight_level()
277 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, in dce_abm_init()
303 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_level()
321 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_immediate_disable()
Ddce_dmcu.c72 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dce_dmcu_load_iram()
84 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dce_dmcu_load_iram()
326 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_get_dmcu_state()
339 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_get_dmcu_state()
353 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_get_dmcu_version()
368 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_get_dmcu_version()
454 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_dmcu_load_iram()
466 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_dmcu_load_iram()
Ddce_mem_input.c158 REG_UPDATE_2(DVMM_PTE_ARB_CONTROL, in dce_mi_program_pte_vm()
238 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2, in dce120_program_stutter_watermark()
242 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce120_program_stutter_watermark()
279 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce_mi_program_display_marks()
308 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce112_mi_program_display_marks()
341 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce120_mi_program_display_marks()
493 REG_UPDATE_2(GRPH_CONTROL, in program_grph_pixel_format()
Ddce_hwseq.c177 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
187 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
Ddce_link_encoder.c298 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, in set_dp_phy_pattern_symbol_error()
318 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, in set_dp_phy_pattern_prbs7()
539 REG_UPDATE_2(DP_SEC_CNTL1, in dce110_psr_program_secondary_packet()
1232 REG_UPDATE_2(DP_MSE_SAT0, in dce110_link_encoder_update_mst_stream_allocation_table()
1246 REG_UPDATE_2(DP_MSE_SAT0, in dce110_link_encoder_update_mst_stream_allocation_table()
1260 REG_UPDATE_2(DP_MSE_SAT1, in dce110_link_encoder_update_mst_stream_allocation_table()
1274 REG_UPDATE_2(DP_MSE_SAT1, in dce110_link_encoder_update_mst_stream_allocation_table()
Ddce_transform.c125 REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0); in setup_scaling_configuration()
788 REG_UPDATE_2(LB_DATA_FORMAT, in dce_transform_set_pixel_storage_depth()
1306 REG_UPDATE_2(DCFE_MEM_PWR_CTRL, in dce110_opp_power_on_regamma_lut()
1310 REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL, in dce110_opp_power_on_regamma_lut()
Ddce_audio.c814 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, in dce_aud_wall_dto_setup()
907 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, in dce_aud_hw_init()
Ddce_aux.c205 REG_UPDATE_2(AUX_SW_CONTROL, in submit_channel_request()
Ddce_clock_source.c895 REG_UPDATE_2(PIXCLK_RESYNC_CNTL, in dce112_program_pixel_clk_resync()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/i2caux/dce110/
Di2c_hw_engine_dce110.c134 REG_UPDATE_2( in release_engine()
180 REG_UPDATE_2( in setup_engine()
228 REG_UPDATE_2( in reset_hw_engine()
Daux_engine_dce110.c234 REG_UPDATE_2(AUX_SW_CONTROL, in submit_channel_request()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_hpd.c110 REG_UPDATE_2(toggle_filt_cntl, in set_config()
Dhw_ddc.c179 REG_UPDATE_2(ddc_setup, in set_config()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c204 REG_UPDATE_2(DCHUB_FB_LOCATION, in dce120_update_dchub()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h235 #define REG_UPDATE_2(reg, f1, v1, f2, v2) \ macro