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Searched refs:REG_UPDATE (Results 1 – 25 of 30) sorted by relevance

12

/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c76 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in dce110_update_generic_info_packet()
96 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in dce110_update_generic_info_packet()
101 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
154 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
158 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
162 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
166 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
[all …]
Ddce_dmcu.c98 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); in dce_get_dmcu_psr_state()
111 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); in dce_get_dmcu_psr_state()
130 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
133 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
137 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_set_psr_enable()
180 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
184 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
188 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
192 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
209 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
[all …]
Ddce_ipp.c49 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_position()
53 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
64 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_position()
75 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_attributes()
134 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_attributes()
144 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
160 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
164 REG_UPDATE(INPUT_GAMMA_CONTROL, in dce_ipp_program_prescale()
184 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); in dce_ipp_program_input_lut()
213 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_ipp_program_input_lut()
[all …]
Ddce_abm.c183 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); in driver_set_backlight_level()
186 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, in driver_set_backlight_level()
216 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dmcu_set_backlight_level()
223 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit); in dmcu_set_backlight_level()
231 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); in dmcu_set_backlight_level()
234 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dmcu_set_backlight_level()
268 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL, in dce_abm_init()
271 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL, in dce_abm_init()
274 REG_UPDATE(BL1_PWM_USER_LEVEL, in dce_abm_init()
308 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_set_level()
[all …]
Ddce_hwseq.c43 REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst], in dce_enable_fe_clock()
117 REG_UPDATE(BLND_CONTROL[blnd_inst], in dce_set_blender_mode()
132 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, in dce_disable_sram_shut_down()
140 REG_UPDATE(DCFEV_CLOCK_CONTROL, in dce_underlay_clock_enable()
171 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
181 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
192 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
Ddce_mem_input.c150 REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, in dce_mi_program_pte_vm()
169 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_urgency_watermark()
183 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in dce120_program_urgency_watermark()
202 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_nbp_watermark()
210 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, in program_nbp_watermark()
215 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_nbp_watermark()
223 REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, in program_nbp_watermark()
234 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in dce120_program_stutter_watermark()
252 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_stutter_watermark()
256 REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, in program_stutter_watermark()
[all …]
Ddce_opp.c173 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
206 REG_UPDATE(FMT_DITHER_RAND_R_SEED, in set_spatial_dither()
209 REG_UPDATE(FMT_DITHER_RAND_G_SEED, in set_spatial_dither()
212 REG_UPDATE(FMT_DITHER_RAND_B_SEED, in set_spatial_dither()
302 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
311 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
441 REG_UPDATE(FMT_CONTROL, in program_formatter_420_memory()
445 REG_UPDATE(CONTROL, in program_formatter_420_memory()
494 REG_UPDATE(FMT_CONTROL, in program_formatter_reset_dig_resync_fifo()
Ddce_link_encoder.c139 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
160 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); in disable_prbs_mode()
229 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); in set_link_training_complete()
403 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
407 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
417 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
438 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); in set_dp_phy_pattern_passthrough_mode()
485 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); in configure_encoder()
516 REG_UPDATE(DP_DPHY_FAST_TRAINING, in dce110_psr_program_dp_dphy_fast_training()
519 REG_UPDATE(DP_DPHY_FAST_TRAINING, in dce110_psr_program_dp_dphy_fast_training()
[all …]
Ddce_audio.c819 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, in dce_aud_wall_dto_setup()
823 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, in dce_aud_wall_dto_setup()
841 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, in dce_aud_wall_dto_setup()
844 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, in dce_aud_wall_dto_setup()
853 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, in dce_aud_wall_dto_setup()
857 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, in dce_aud_wall_dto_setup()
860 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, in dce_aud_wall_dto_setup()
903 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, in dce_aud_hw_init()
Ddce_transform.c127 REG_UPDATE(SCL_MODE, SCL_MODE, 0); in setup_scaling_configuration()
136 REG_UPDATE(SCL_MODE, SCL_MODE, 1); in setup_scaling_configuration()
138 REG_UPDATE(SCL_MODE, SCL_MODE, 2); in setup_scaling_configuration()
141 REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1); in setup_scaling_configuration()
397 REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1); in dce_transform_set_scaler()
399 REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en); in dce_transform_set_scaler()
1148 REG_UPDATE(DCFE_MEM_PWR_CTRL, in program_pwl()
1151 REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, in program_pwl()
1181 REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK, in program_pwl()
1202 REG_UPDATE(DCFE_MEM_PWR_CTRL, in program_pwl()
[all …]
Ddce_clock_source.c825 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
838 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
842 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
846 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
850 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
899 REG_UPDATE(PIXCLK_RESYNC_CNTL, in dce112_program_pixel_clk_resync()
923 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); in dce110_program_pix_clk()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c67 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in enc1_update_generic_info_packet()
86 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in enc1_update_generic_info_packet()
90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in enc1_update_generic_info_packet()
122 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
[all …]
Ddcn10_opp.c166 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); in opp1_set_pixel_encoding()
169 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1); in opp1_set_pixel_encoding()
172 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); in opp1_set_pixel_encoding()
284 REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0); in opp1_program_fmt()
318 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0); in opp1_program_stereo()
320 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width); in opp1_program_stereo()
328 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size); in opp1_program_stereo()
330 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size); in opp1_program_stereo()
350 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width); in opp1_program_oppbuf()
358 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation); in opp1_program_oppbuf()
[all …]
Ddcn10_dpp.c283 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); in dpp1_set_degamma_format_float()
284 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); in dpp1_set_degamma_format_float()
286 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); in dpp1_set_degamma_format_float()
287 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); in dpp1_set_degamma_format_float()
393 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
414 REG_UPDATE(CURSOR_CONTROL, in dpp1_cnv_setup()
416 REG_UPDATE(CURSOR0_CONTROL, in dpp1_cnv_setup()
433 REG_UPDATE(CURSOR0_COLOR0, in dpp1_set_cursor_attributes()
435 REG_UPDATE(CURSOR0_COLOR1, in dpp1_set_cursor_attributes()
457 REG_UPDATE(CURSOR0_CONTROL, in dpp1_set_cursor_position()
[all …]
Ddcn10_dpp_cm.c385 REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, in dpp1_cm_configure_regamma_lut()
387 REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, in dpp1_cm_configure_regamma_lut()
618 REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8); in dpp1_enable_cm_block()
619 REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0); in dpp1_enable_cm_block()
632 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0); in dpp1_set_degamma()
635 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1); in dpp1_set_degamma()
638 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2); in dpp1_set_degamma()
653 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); in dpp1_degamma_ram_select()
655 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4); in dpp1_degamma_ram_select()
689 REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0); in dpp1_program_degamma_lut()
[all …]
Ddcn10_link_encoder.c110 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
131 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); in disable_prbs_mode()
200 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); in set_link_training_complete()
371 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
375 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
385 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
406 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); in set_dp_phy_pattern_passthrough_mode()
452 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); in configure_encoder()
461 REG_UPDATE(DP_DPHY_FAST_TRAINING, in dcn10_psr_program_dp_dphy_fast_training()
464 REG_UPDATE(DP_DPHY_FAST_TRAINING, in dcn10_psr_program_dp_dphy_fast_training()
[all …]
Ddcn10_hubbub.c466 REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL, in hubbub1_program_watermarks()
468 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, in hubbub1_program_watermarks()
495 REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, in hubbub1_update_dchub()
498 REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, in hubbub1_update_dchub()
501 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, in hubbub1_update_dchub()
504 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, in hubbub1_update_dchub()
507 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, in hubbub1_update_dchub()
514 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, in hubbub1_update_dchub()
517 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, in hubbub1_update_dchub()
520 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, in hubbub1_update_dchub()
[all …]
Ddcn10_hubp.c74 REG_UPDATE(DCHUBP_CNTL, in hubp1_disconnect()
77 REG_UPDATE(CURSOR_CONTROL, in hubp1_disconnect()
86 REG_UPDATE(DCHUBP_CNTL, in hubp1_disable_control()
107 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); in hubp1_set_hubp_blank_en()
253 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
257 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
262 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
268 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
272 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
277 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
[all …]
Ddcn10_mpc.c210 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); in mpc1_insert_plane()
214 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH); in mpc1_insert_plane()
223 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); in mpc1_insert_plane()
234 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], in mpc1_insert_plane()
279 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); in mpc1_remove_mpcc()
283 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); in mpc1_remove_mpcc()
303 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], in mpc1_remove_mpcc()
363 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf); in mpc1_mpc_init()
Ddcn10_optc.c237 REG_UPDATE(OTG_H_SYNC_A_CNTL, in optc1_program_timing()
303 REG_UPDATE(OTG_V_SYNC_A_CNTL, in optc1_program_timing()
320 REG_UPDATE(OTG_INTERLACE_CONTROL, in optc1_program_timing()
326 REG_UPDATE(OTG_INTERLACE_CONTROL, in optc1_program_timing()
331 REG_UPDATE(CONTROL, in optc1_program_timing()
358 REG_UPDATE(OTG_H_TIMING_CNTL, in optc1_program_timing()
369 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, in optc1_set_blank_data_double_buffer()
480 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, in optc1_enable_crtc()
484 REG_UPDATE(CONTROL, in optc1_enable_crtc()
507 REG_UPDATE(CONTROL, in optc1_disable_crtc()
[all …]
Ddcn10_hw_sequencer.c363 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); in enable_power_gating_plane()
364 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); in enable_power_gating_plane()
365 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); in enable_power_gating_plane()
366 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); in enable_power_gating_plane()
369 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); in enable_power_gating_plane()
370 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); in enable_power_gating_plane()
371 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); in enable_power_gating_plane()
372 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); in enable_power_gating_plane()
404 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1); in disable_vga()
405 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1); in disable_vga()
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_gpio.c54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
55 REG_UPDATE(A_reg, A, gpio->store.a); in restore_registers()
56 REG_UPDATE(EN_reg, EN, gpio->store.en); in restore_registers()
107 REG_UPDATE(A_reg, A, value); in dal_hw_gpio_set_value()
114 REG_UPDATE(EN_reg, EN, ~value); in dal_hw_gpio_set_value()
151 REG_UPDATE(EN_reg, EN, 0); in dal_hw_gpio_config_mode()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
157 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
163 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c208 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
211 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
214 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
219 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
222 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
225 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
230 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
233 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
236 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/bios/
Dbios_parser_helper.c69 REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1); in bios_set_scratch_acc_mode_change()
78 REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state); in bios_set_scratch_critical_state()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/i2caux/dce110/
Daux_engine_dce110.c77 REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1); in release_engine()
167 REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1); in acquire_engine()
272 REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1); in submit_channel_request()
275 REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1); in submit_channel_request()

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