Home
last modified time | relevance | path

Searched refs:REG_SET_FIELD (Results 1 – 25 of 41) sorted by relevance

12

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c110 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
111 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
112 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
114 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
116 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v1_0_init_tlb_regs()
117 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
119 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
130 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
131 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs()
133 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_0_init_cache_regs()
[all …]
Dmmhub_v1_0.c111 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
123 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
124 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
125 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
129 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in mmhub_v1_0_init_tlb_regs()
130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in mmhub_v1_0_init_tlb_regs()
143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
144 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_0_init_cache_regs()
[all …]
Dgmc_v7_0.c97 blackout = REG_SET_FIELD(blackout, in gmc_v7_0_mc_stop()
111 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_resume()
114 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v7_0_mc_resume()
115 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v7_0_mc_resume()
277 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v7_0_mc_program()
282 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v7_0_mc_program()
302 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v7_0_mc_program()
519 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
521 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
523 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
[all …]
Ddce_v10_0.c239 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v10_0_page_flip()
307 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v10_0_hpd_set_polarity()
309 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v10_0_hpd_set_polarity()
341 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); in dce_v10_0_hpd_init()
347 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v10_0_hpd_init()
351 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v10_0_hpd_init()
354 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v10_0_hpd_init()
386 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v10_0_hpd_fini()
437 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v10_0_set_vga_render_state()
439 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v10_0_set_vga_render_state()
[all …]
Dgmc_v8_0.c182 blackout = REG_SET_FIELD(blackout, in gmc_v8_0_mc_stop()
196 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume()
199 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume()
200 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v8_0_mc_resume()
446 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program()
451 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v8_0_mc_program()
482 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v8_0_mc_program()
722 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
724 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
726 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
[all …]
Ddce_v11_0.c257 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v11_0_page_flip()
325 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v11_0_hpd_set_polarity()
327 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v11_0_hpd_set_polarity()
359 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); in dce_v11_0_hpd_init()
365 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v11_0_hpd_init()
369 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v11_0_hpd_init()
372 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v11_0_hpd_init()
403 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v11_0_hpd_fini()
453 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v11_0_set_vga_render_state()
455 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v11_0_set_vga_render_state()
[all …]
Dnbio_v6_1.c82 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v6_1_sdma_doorbell_range()
83 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); in nbio_v6_1_sdma_doorbell_range()
85 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); in nbio_v6_1_sdma_doorbell_range()
103 …tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN… in nbio_v6_1_enable_doorbell_selfring_aperture()
104 …REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1)… in nbio_v6_1_enable_doorbell_selfring_aperture()
105 …REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); in nbio_v6_1_enable_doorbell_selfring_aperture()
123 …ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index… in nbio_v6_1_ih_doorbell_range()
124 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); in nbio_v6_1_ih_doorbell_range()
126 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); in nbio_v6_1_ih_doorbell_range()
141 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in nbio_v6_1_ih_control()
[all …]
Dcz_ih.c63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts()
83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
119 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in cz_ih_irq_init()
121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in cz_ih_irq_init()
128 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init()
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in cz_ih_irq_init()
[all …]
Diceland_ih.c63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts()
83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
119 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in iceland_ih_irq_init()
121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in iceland_ih_irq_init()
128 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init()
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in iceland_ih_irq_init()
[all …]
Dvega10_ih.c49 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in vega10_ih_enable_interrupts()
50 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in vega10_ih_enable_interrupts()
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in vega10_ih_disable_interrupts()
67 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in vega10_ih_disable_interrupts()
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); in vega10_ih_irq_init()
109 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); in vega10_ih_irq_init()
112 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in vega10_ih_irq_init()
113 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in vega10_ih_irq_init()
114 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_irq_init()
116 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in vega10_ih_irq_init()
[all …]
Dtonga_ih.c62 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts()
63 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
79 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts()
80 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
115 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in tonga_ih_irq_init()
117 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init()
128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in tonga_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in tonga_ih_irq_init()
[all …]
Dnbio_v7_0.c93 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_0_sdma_doorbell_range()
94 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range); in nbio_v7_0_sdma_doorbell_range()
96 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); in nbio_v7_0_sdma_doorbell_range()
119 …ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index… in nbio_v7_0_ih_doorbell_range()
120 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); in nbio_v7_0_ih_doorbell_range()
122 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); in nbio_v7_0_ih_doorbell_range()
232 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in nbio_v7_0_ih_control()
234 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in nbio_v7_0_ih_control()
Ddce_v6_0.c1110 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, in dce_v6_0_audio_select_pin()
1141 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v6_0_audio_write_latency_fields()
1143 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v6_0_audio_write_latency_fields()
1146 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v6_0_audio_write_latency_fields()
1148 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v6_0_audio_write_latency_fields()
1187 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
1189 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
1193 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
1196 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
1200 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
[all …]
Dgmc_v6_0.c81 blackout = REG_SET_FIELD(blackout, in gmc_v6_0_mc_stop()
96 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v6_0_mc_resume()
99 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v6_0_mc_resume()
100 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v6_0_mc_resume()
424 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
426 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
428 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
430 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
432 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
434 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
[all …]
Dsdma_v3_0.c452 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
454 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
521 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop()
524 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v3_0_gfx_stop()
583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
625 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_enable()
627 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v3_0_enable()
[all …]
Dsdma_v2_4.c277 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
279 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
346 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop()
349 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v2_4_gfx_stop()
389 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_enable()
391 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v2_4_enable()
434 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
436 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v2_4_gfx_resume()
437 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v2_4_gfx_resume()
454 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v2_4_gfx_resume()
[all …]
Dgfx_v9_0.c830 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); in gfx_v9_0_init_lbpw()
831 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); in gfx_v9_0_init_lbpw()
832 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); in gfx_v9_0_init_lbpw()
847 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_0_init_lbpw()
848 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_0_init_lbpw()
1376 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, in gfx_v9_0_ngg_en()
1378 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, in gfx_v9_0_ngg_en()
1382 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, in gfx_v9_0_ngg_en()
1384 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, in gfx_v9_0_ngg_en()
1390 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); in gfx_v9_0_ngg_en()
[all …]
Dgfx_v8_0.c1691 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1717 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1743 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1763 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); in gfx_v8_0_do_edc_gpr_workarounds()
1764 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1768 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; in gfx_v8_0_do_edc_gpr_workarounds()
1973 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); in gfx_v8_0_gpu_early_init()
1976 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); in gfx_v8_0_gpu_early_init()
1979 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); in gfx_v8_0_gpu_early_init()
3554 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
[all …]
Dsdma_v4_0.c506 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_0_gfx_stop()
509 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v4_0_gfx_stop()
568 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable()
603 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_0_enable()
637 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_gfx_resume()
639 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v4_0_gfx_resume()
640 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v4_0_gfx_resume()
657 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v4_0_gfx_resume()
676 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); in sdma_v4_0_gfx_resume()
677 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, in sdma_v4_0_gfx_resume()
[all …]
Damdgpu_amdkfd_gfx_v8.c337 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, in kgd_hqd_load()
365 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, in kgd_hqd_load()
379 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); in kgd_hqd_load()
448 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL, in kgd_hqd_sdma_load()
453 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, in kgd_hqd_sdma_load()
458 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, in kgd_hqd_sdma_load()
479 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
748 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
750 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
752 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
Dmxgpu_vi.c325 reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1); in xgpu_vi_mailbox_send_ack()
347 reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, in xgpu_vi_mailbox_set_valid()
358 reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0, in xgpu_vi_mailbox_trans_msg()
505 tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN, in xgpu_vi_set_mailbox_ack_irq()
534 tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN, in xgpu_vi_set_mailbox_rcv_irq()
Damdgpu_amdkfd_gfx_v9.c424 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, in kgd_hqd_load()
439 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, in kgd_hqd_load()
484 REG_SET_FIELD(m->cp_hqd_eop_rptr, in kgd_hqd_load()
487 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); in kgd_hqd_load()
558 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, in kgd_hqd_sdma_load()
565 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, in kgd_hqd_sdma_load()
594 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
934 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
936 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
938 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
Dgmc_v9_0.c299 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, in gmc_v9_0_get_invalidate_req()
301 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); in gmc_v9_0_get_invalidate_req()
302 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gmc_v9_0_get_invalidate_req()
303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gmc_v9_0_get_invalidate_req()
304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gmc_v9_0_get_invalidate_req()
305 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gmc_v9_0_get_invalidate_req()
306 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gmc_v9_0_get_invalidate_req()
307 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, in gmc_v9_0_get_invalidate_req()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_thermal.c142 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
145 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
278 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega10_fan_ctrl_set_fan_speed_percent()
325 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_set_fan_speed_rpm()
382 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); in vega10_thermal_set_temperature_range()
383 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); in vega10_thermal_set_temperature_range()
384 …val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CE… in vega10_thermal_set_temperature_range()
385 …val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CEN… in vega10_thermal_set_temperature_range()
[all …]
Dvega12_thermal.c190 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); in vega12_thermal_set_temperature_range()
191 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); in vega12_thermal_set_temperature_range()
192 …val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CE… in vega12_thermal_set_temperature_range()
193 …val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CEN… in vega12_thermal_set_temperature_range()

12