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Searched refs:REG_SET_2 (Results 1 – 19 of 19) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_dscl.c107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0, in dpp1_dscl_set_overscan()
111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0, in dpp1_dscl_set_overscan()
124 REG_SET_2(OTG_H_BLANK, 0, in dpp1_dscl_set_otg_blank()
128 REG_SET_2(OTG_V_BLANK, 0, in dpp1_dscl_set_otg_blank()
222 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb()
380 REG_SET_2(SCL_MODE, scl_mode, in dpp1_dscl_set_scl_filter()
542 REG_SET_2(SCL_BLACK_OFFSET, 0, in dpp1_dscl_set_scaler_auto_scale()
547 REG_SET_2(SCL_BLACK_OFFSET, 0, in dpp1_dscl_set_scaler_auto_scale()
584 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
590 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, in dpp1_dscl_set_manual_ratio_init()
[all …]
Ddcn10_hubp.c539 REG_SET_2(BLANK_OFFSET_0, 0, in hubp1_program_deadline()
549 REG_SET_2(DST_AFTER_SCALER, 0, in hubp1_program_deadline()
554 REG_SET_2(PREFETCH_SETTINS, 0, in hubp1_program_deadline()
558 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp1_program_deadline()
562 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp1_program_deadline()
590 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp1_program_deadline()
594 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp1_program_deadline()
626 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp1_program_deadline()
630 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp1_program_deadline()
717 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_system_aperture_settings()
[all …]
Ddcn10_cm_common.c56 REG_SET_2(cur_csc_reg, 0, in cm_helper_program_color_matrices()
73 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_xfer_func()
76 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_xfer_func()
79 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_xfer_func()
92 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_xfer_func()
98 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_xfer_func()
104 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_xfer_func()
Ddcn10_optc.c75 REG_SET_2(OTG_VUPDATE_PARAM, 0, in optc1_program_global_sync()
166 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, in optc1_program_vline_interrupt()
820 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, in optc1_set_static_screen_control()
1018 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()
1030 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()
Ddcn10_stream_encoder.c416 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, in enc1_stream_encoder_dp_set_stream_attribute()
440 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, in enc1_stream_encoder_dp_set_stream_attribute()
455 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, in enc1_stream_encoder_dp_set_stream_attribute()
623 REG_SET_2(DP_MSE_RATE_CNTL, 0, in enc1_stream_encoder_set_mst_bandwidth()
Ddcn10_dpp_cm.c531 REG_SET_2(CM_BNS_VALUES_R, 0, in dpp1_program_bias_and_scale()
535 REG_SET_2(CM_BNS_VALUES_G, 0, in dpp1_program_bias_and_scale()
539 REG_SET_2(CM_BNS_VALUES_B, 0, in dpp1_program_bias_and_scale()
Ddcn10_link_encoder.c157 REG_SET_2(DP_DPHY_SYM2, 0, in program_pattern_symbols()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.c131 REG_SET_2(SCL_TAP_CONTROL, 0, in setup_scaling_configuration()
172 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, in program_overscan()
175 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, in program_overscan()
239 REG_SET_2(VIEWPORT_START, 0, in program_viewport()
243 REG_SET_2(VIEWPORT_SIZE, 0, in program_viewport()
293 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in program_scl_ratios_inits()
297 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in program_scl_ratios_inits()
331 REG_SET_2(LB_MEMORY_CTRL, 0, in dce_transform_set_scaler()
443 REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0, in set_clamp()
447 REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0, in set_clamp()
[all …]
Ddce_opp.c328 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
336 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
341 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
346 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
352 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
357 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, in dce110_opp_set_clamping()
361 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, in dce110_opp_set_clamping()
365 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, in dce110_opp_set_clamping()
Ddce_ipp.c55 REG_SET_2(CUR_POSITION, 0, in dce_ipp_cursor_set_position()
59 REG_SET_2(CUR_HOT_SPOT, 0, in dce_ipp_cursor_set_position()
117 REG_SET_2(CUR_SIZE, 0, in dce_ipp_cursor_set_attributes()
147 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, in dce_ipp_program_prescale()
151 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, in dce_ipp_program_prescale()
155 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, in dce_ipp_program_prescale()
Ddce_hwseq.c71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
Ddce_mem_input.c172 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in program_urgency_watermark()
186 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce120_program_urgency_watermark()
190 REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0, in dce120_program_urgency_watermark()
451 REG_SET_2(GRPH_SWAP_CNTL, 0, in program_grph_pixel_format()
657 REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0, in program_sec_addr()
Ddce_stream_encoder.c455 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, in dce110_stream_encoder_dp_set_stream_attribute()
482 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, in dce110_stream_encoder_dp_set_stream_attribute()
499 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, in dce110_stream_encoder_dp_set_stream_attribute()
692 REG_SET_2(DP_MSE_RATE_CNTL, 0, in dce110_stream_encoder_set_mst_bandwidth()
Ddce_aux.c216 value = REG_SET_2(AUX_SW_DATA, value, in submit_channel_request()
Ddce_link_encoder.c186 REG_SET_2(DP_DPHY_SYM2, 0, in program_pattern_symbols()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/i2caux/dce110/
Di2c_hw_engine_dce110.c317 value = REG_SET_2(DC_I2C_DATA, 0, in process_transaction()
325 REG_SET_2(DC_I2C_DATA, value, in process_transaction()
Daux_engine_dce110.c245 value = REG_SET_2(AUX_SW_DATA, value, in submit_channel_request()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_ddc.c95 REG_SET_2(gpio.MASK_reg, regval, in set_config()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ macro