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Searched refs:REG_SET (Results 1 – 25 of 45) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c317 REG_SET(DCSURF_FLIP_CONTROL, 0, in hubp1_program_surface_flip_and_addr()
342 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
346 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
351 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
355 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
371 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
375 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
379 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
383 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
388 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
[all …]
Ddcn10_dpp_cm.c131 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
185 REG_SET( in program_gamut_remap()
232 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
266 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
354 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
367 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); in dpp1_cm_program_regamma_lut()
368 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); in dpp1_cm_program_regamma_lut()
369 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); in dpp1_cm_program_regamma_lut()
371 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); in dpp1_cm_program_regamma_lut()
372 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); in dpp1_cm_program_regamma_lut()
[all …]
Ddcn10_mpc.c54 REG_SET(MPCC_BG_R_CR[mpcc_id], 0, in mpc1_set_bg_color()
56 REG_SET(MPCC_BG_G_Y[mpcc_id], 0, in mpc1_set_bg_color()
58 REG_SET(MPCC_BG_B_CB[mpcc_id], 0, in mpc1_set_bg_color()
209 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); in mpc1_insert_plane()
213 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
216 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
217 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
231 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); in mpc1_insert_plane()
297 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
301 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
[all …]
Ddcn10_optc.c72 REG_SET(OTG_VSTARTUP_PARAM, 0, in optc1_program_global_sync()
79 REG_SET(OTG_VREADY_PARAM, 0, in optc1_program_global_sync()
87 REG_SET(OTG_STEREO_CONTROL, 0, in optc1_disable_stereo()
203 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
250 REG_SET(OTG_V_TOTAL, 0, in optc1_program_timing()
256 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_program_timing()
258 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_program_timing()
296 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, in optc1_program_timing()
619 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc1_lock()
621 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc1_lock()
[all …]
Ddcn10_cm_common.c83 REG_SET(reg->start_slope_cntl_b, 0, in cm_helper_program_xfer_func()
85 REG_SET(reg->start_slope_cntl_g, 0, in cm_helper_program_xfer_func()
87 REG_SET(reg->start_slope_cntl_r, 0, in cm_helper_program_xfer_func()
90 REG_SET(reg->start_end_cntl1_b, 0, in cm_helper_program_xfer_func()
96 REG_SET(reg->start_end_cntl1_g, 0, in cm_helper_program_xfer_func()
102 REG_SET(reg->start_end_cntl1_r, 0, in cm_helper_program_xfer_func()
Ddcn10_opp.c96 REG_SET(FMT_DITHER_RAND_R_SEED, 0, in opp1_set_spatial_dither()
99 REG_SET(FMT_DITHER_RAND_G_SEED, 0, in opp1_set_spatial_dither()
102 REG_SET(FMT_DITHER_RAND_B_SEED, 0, in opp1_set_spatial_dither()
Ddcn10_dpp.c128 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in dpp_set_gamut_remap_bypass()
260 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); in dpp1_cm_set_regamma_pwl()
391 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_cnv_setup()
Ddcn10_dpp_dscl.c567 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in dpp1_dscl_set_manual_ratio_init()
570 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in dpp1_dscl_set_manual_ratio_init()
573 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, in dpp1_dscl_set_manual_ratio_init()
576 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, in dpp1_dscl_set_manual_ratio_init()
Ddcn10_stream_encoder.c410 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); in enc1_stream_encoder_dp_set_stream_attribute()
1174 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in enc1_se_audio_setup()
1271 REG_SET(DP_SEC_AUD_N, 0, in enc1_se_setup_dp_audio()
1275 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, in enc1_se_setup_dp_audio()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_ipp.c127 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
130 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
178 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
181 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
193 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
197 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
200 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
203 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
210 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
Ddce_transform.c120 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in setup_scaling_configuration()
144 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); in setup_scaling_configuration()
199 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); in program_multi_taps_filter()
287 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
290 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
358 REG_SET(SCL_VERT_FILTER_CONTROL, 0, in dce_transform_set_scaler()
373 REG_SET(SCL_HORZ_FILTER_CONTROL, 0, in dce_transform_set_scaler()
538 REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits); in set_round()
744 REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode); in set_denormalization()
824 REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1); in program_gamut_remap()
[all …]
Ddce_mem_input.c413 REG_SET(GRPH_X_START, 0, in program_size_and_rotation()
416 REG_SET(GRPH_Y_START, 0, in program_size_and_rotation()
419 REG_SET(GRPH_X_END, 0, in program_size_and_rotation()
422 REG_SET(GRPH_Y_END, 0, in program_size_and_rotation()
425 REG_SET(GRPH_PITCH, 0, in program_size_and_rotation()
428 REG_SET(HW_ROTATION, 0, in program_size_and_rotation()
594 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, in dce_mi_allocate_dmif()
631 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, in dce_mi_free_dmif()
653 REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0, in program_sec_addr()
667 REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in program_pri_addr()
[all …]
Ddce_audio.c62 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, in write_indirect_azalia_reg()
66 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, in write_indirect_azalia_reg()
80 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, in read_indirect_azalia_reg()
/Linux-v4.19/arch/arm/mach-imx/
Danatop.c22 #define REG_SET 0x4 macro
54 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
60 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
66 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
72 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/Linux-v4.19/drivers/thermal/
Dimx_thermal.c26 #define REG_SET 0x4 macro
233 regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, in imx_set_panic_temp()
253 regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, in imx_set_alarm_temp()
278 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_get_temp()
296 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_get_temp()
364 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_set_mode()
374 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_set_mode()
706 regmap_write(map, data->socdata->low_alarm_ctrl + REG_SET, in imx_thermal_probe()
741 regmap_write(map, IMX6_MISC0 + REG_SET, in imx_thermal_probe()
743 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_ddc.c113 REG_SET(gpio.MASK_reg, regval, in set_config()
122 REG_SET(gpio.MASK_reg, regval, in set_config()
151 REG_SET(gpio.MASK_reg, regval, in set_config()
/Linux-v4.19/drivers/gpu/drm/radeon/
Dr300d.h61 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
62 REG_SET(PACKET0_COUNT, (n)))
63 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
65 REG_SET(PACKET3_IT_OPCODE, (op)) | \
66 REG_SET(PACKET3_COUNT, (n)))
Drv515d.h201 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
202 REG_SET(PACKET0_COUNT, (n)))
203 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n)))
Dr100d.h60 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
61 REG_SET(PACKET0_COUNT, (n)))
62 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
64 REG_SET(PACKET3_IT_OPCODE, (op)) | \
65 REG_SET(PACKET3_COUNT, (n)))
/Linux-v4.19/drivers/gpu/drm/mxsfb/
Dmxsfb_crtc.c135 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
142 writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
219 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); in mxsfb_crtc_mode_set_nofb()
Dmxsfb_regs.h20 #define REG_SET 4 macro
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/i2caux/dce110/
Daux_engine_dce110.c249 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
253 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
265 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h45 #ifdef REG_SET
46 #undef REG_SET
63 #define REG_SET(reg_name, initial_val, field, val) \ macro
385 REG_SET(reg, val, field, value2); }
390 REG_SET(reg, val, f2, v2); }
394 val = REG_SET(reg, val, f2, v2); \
395 REG_SET(reg, val, f3, v3); }
/Linux-v4.19/drivers/gpio/
Dgpio-ingenic.c33 #define REG_SET(x) ((x) + 0x4) macro
63 reg = REG_SET(reg); in gpio_ingenic_set_bit()
/Linux-v4.19/drivers/video/fbdev/
Dmxsfb.c55 #define REG_SET 4 macro
353 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
360 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
435 writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); in mxsfb_set_par()

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