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Searched refs:REG_GET_FIELD (Results 1 – 25 of 25) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgmc_v7_0.c93 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v7_0_mc_stop()
199 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
222 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
228 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
329 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v7_0_mc_init()
335 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
761 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
762 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
768 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
773 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
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Dgmc_v8_0.c178 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v8_0_mc_stop()
295 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
318 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
324 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
509 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
515 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
983 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v8_0_vm_decode_fault()
984 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
990 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
995 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
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Dgmc_v9_0.c583 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap, in gmc_v9_0_ecc_available()
601 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG, in gmc_v9_0_ecc_available()
620 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, in gmc_v9_0_ecc_available()
622 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, in gmc_v9_0_ecc_available()
812 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v9_0_get_vbios_fb_size()
820 size = (REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
822 REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
830 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v9_0_get_vbios_fb_size()
831 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v9_0_get_vbios_fb_size()
Dgmc_v6_0.c77 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v6_0_mc_stop()
639 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v6_0_vm_decode_fault()
640 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
645 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
650 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
829 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v6_0_get_vbios_fb_size()
833 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v6_0_get_vbios_fb_size()
834 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v6_0_get_vbios_fb_size()
Damdgpu_amdkfd_gfx_v7.c159 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
161 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
608 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
612 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
613 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
620 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
939 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
Dcz_ih.c194 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in cz_ih_get_wptr()
360 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_is_idle()
375 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_wait_for_idle()
Diceland_ih.c194 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in iceland_ih_get_wptr()
360 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_is_idle()
375 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_wait_for_idle()
Damdgpu_amdkfd_gfx_v8.c116 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
118 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
605 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
609 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
610 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
617 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
Dtonga_ih.c205 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in tonga_ih_get_wptr()
383 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_is_idle()
398 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_wait_for_idle()
Dgfx_v8_0.c1935 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1936 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1939 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1940 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1959 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); in gfx_v8_0_gpu_early_init()
3584 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); in gfx_v8_0_get_rb_active_bitmap()
5195 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) in gfx_v8_0_is_idle()
5240 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) in gfx_v8_0_check_soft_reset()
5244 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) || in gfx_v8_0_check_soft_reset()
5245 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) || in gfx_v8_0_check_soft_reset()
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Dvi.c335 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) in vi_get_xclk()
339 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) in vi_get_xclk()
458 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER)) in vi_detect_hw_virtualization()
461 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE)) in vi_detect_hw_virtualization()
Dsdma_v3_0.c1337 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || in sdma_v3_0_pre_soft_reset()
1338 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { in sdma_v3_0_pre_soft_reset()
1356 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || in sdma_v3_0_post_soft_reset()
1357 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { in sdma_v3_0_post_soft_reset()
Dgfx_v9_0.c1223 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1232 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1237 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1242 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1247 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
1252 REG_GET_FIELD( in gfx_v9_0_gpu_early_init()
3309 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), in gfx_v9_0_is_idle()
3356 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) in gfx_v9_0_soft_reset()
3493 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) in gfx_v9_0_enter_rlc_safe_mode()
Dvega10_ih.c203 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in vega10_ih_get_wptr()
Duvd_v6_0.c1151 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || in uvd_v6_0_check_soft_reset()
1152 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || in uvd_v6_0_check_soft_reset()
Ddce_v11_0.c423 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { in dce_v11_0_is_display_hung()
503 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_disable_dce()
650 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v11_0_line_buffer_adjust()
684 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in cik_get_number_of_dram_channels()
Ddce_v10_0.c407 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { in dce_v10_0_is_display_hung()
477 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v10_0_disable_dce()
624 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v10_0_line_buffer_adjust()
658 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in cik_get_number_of_dram_channels()
Duvd_v7_0.c1457 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1458 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
Damdgpu_amdkfd_gfx_v9.c461 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
Dgfx_v7_0.c4412 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v7_0_gpu_early_init()
4413 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v7_0_gpu_early_init()
4416 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v7_0_gpu_early_init()
4417 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v7_0_gpu_early_init()
Dgfx_v6_0.c1312 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); in gfx_v6_0_get_rb_active_bitmap()
1518 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; in gfx_v6_0_get_cu_enabled()
Damdgpu.h1653 #define REG_GET_FIELD(value, reg, field) \ macro
Ddce_v8_0.c417 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v8_0_disable_dce()
Ddce_v6_0.c1077 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, in dce_v6_0_audio_get_connected_pins()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_thermal.c105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
267 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_percent()