Searched refs:REG_DSI_28nm_PHY_PLL_LKDET_CFG2 (Results 1 – 2 of 2) sorted by relevance
222 pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); in dsi_pll_28nm_clk_set_rate()353 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, in dsi_pll_28nm_enable_seq_hpm()355 pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); in dsi_pll_28nm_enable_seq_hpm()426 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); in dsi_pll_28nm_enable_seq_lp()427 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); in dsi_pll_28nm_enable_seq_lp()
1067 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 macro
