Searched refs:REG_DSI_28nm_8960_PHY_PLL_CTRL_2 (Results 1 – 2 of 2) sorted by relevance
134 val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); in dsi_pll_28nm_clk_set_rate()138 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, in dsi_pll_28nm_clk_set_rate()184 temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; in dsi_pll_28nm_clk_recalc_rate()
759 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 macro
