Searched refs:REG_DSI_14nm_PHY_CMN_CLK_CFG0 (Results 1 – 2 of 2) sorted by relevance
697 val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; in dsi_pll_14nm_postdiv_recalc_rate()739 val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); in dsi_pll_14nm_postdiv_set_rate()743 pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); in dsi_pll_14nm_postdiv_set_rate()752 pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); in dsi_pll_14nm_postdiv_set_rate()810 data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); in dsi_pll_14nm_save_state()842 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); in dsi_pll_14nm_restore_state()849 pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); in dsi_pll_14nm_restore_state()
1315 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010 macro
