Searched refs:REG_DSI_10nm_PHY_CMN_CLK_CFG1 (Results 1 – 2 of 2) sorted by relevance
383 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_pll_disable_global_clk()384 pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, in dsi_pll_disable_global_clk()392 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_pll_enable_global_clk()393 pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, in dsi_pll_enable_global_clk()535 cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_pll_10nm_save_state()558 val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_pll_10nm_restore_state()561 pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); in dsi_pll_10nm_restore_state()591 pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); in dsi_pll_10nm_set_usecase()733 REG_DSI_10nm_PHY_CMN_CLK_CFG1, in pll_10nm_register()
1569 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014 macro
