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Searched refs:REG (Results 1 – 25 of 126) sorted by relevance

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/Linux-v4.19/drivers/net/ethernet/mscc/
Docelot_regs.c10 REG(ANA_ADVLEARN, 0x009000),
11 REG(ANA_VLANMASK, 0x009004),
12 REG(ANA_PORT_B_DOMAIN, 0x009008),
13 REG(ANA_ANAGEFIL, 0x00900c),
14 REG(ANA_ANEVENTS, 0x009010),
15 REG(ANA_STORMLIMIT_BURST, 0x009014),
16 REG(ANA_STORMLIMIT_CFG, 0x009018),
17 REG(ANA_ISOLATED_PORTS, 0x009028),
18 REG(ANA_COMMUNITY_PORTS, 0x00902c),
19 REG(ANA_AUTOAGE, 0x009030),
[all …]
/Linux-v4.19/tools/perf/arch/s390/util/
Dunwind-libdw.c15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
24 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
25 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
26 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
27 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
28 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
29 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
30 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
31 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
32 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
/Linux-v4.19/tools/perf/arch/arm64/util/
Dunwind-libdw.c13 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
19 dwarf_regs[0] = REG(X0); in libdw__arch_set_initial_registers()
20 dwarf_regs[1] = REG(X1); in libdw__arch_set_initial_registers()
21 dwarf_regs[2] = REG(X2); in libdw__arch_set_initial_registers()
22 dwarf_regs[3] = REG(X3); in libdw__arch_set_initial_registers()
23 dwarf_regs[4] = REG(X4); in libdw__arch_set_initial_registers()
24 dwarf_regs[5] = REG(X5); in libdw__arch_set_initial_registers()
25 dwarf_regs[6] = REG(X6); in libdw__arch_set_initial_registers()
26 dwarf_regs[7] = REG(X7); in libdw__arch_set_initial_registers()
27 dwarf_regs[8] = REG(X8); in libdw__arch_set_initial_registers()
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/Linux-v4.19/tools/perf/arch/powerpc/util/
Dunwind-libdw.c21 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
27 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
28 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
29 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
30 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
31 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
32 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
33 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
34 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
35 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
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/Linux-v4.19/drivers/net/ethernet/apple/
Dmace.h13 #define REG(x) volatile unsigned char x; char x ## _pad[15] macro
16 REG(rcvfifo); /* receive FIFO */
17 REG(xmtfifo); /* transmit FIFO */
18 REG(xmtfc); /* transmit frame control */
19 REG(xmtfs); /* transmit frame status */
20 REG(xmtrc); /* transmit retry count */
21 REG(rcvfc); /* receive frame control */
22 REG(rcvfs); /* receive frame status (4 bytes) */
23 REG(fifofc); /* FIFO frame count */
24 REG(ir); /* interrupt register */
[all …]
/Linux-v4.19/tools/perf/arch/x86/util/
Dunwind-libdw.c14 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
21 dwarf_regs[0] = REG(AX); in libdw__arch_set_initial_registers()
22 dwarf_regs[1] = REG(CX); in libdw__arch_set_initial_registers()
23 dwarf_regs[2] = REG(DX); in libdw__arch_set_initial_registers()
24 dwarf_regs[3] = REG(BX); in libdw__arch_set_initial_registers()
25 dwarf_regs[4] = REG(SP); in libdw__arch_set_initial_registers()
26 dwarf_regs[5] = REG(BP); in libdw__arch_set_initial_registers()
27 dwarf_regs[6] = REG(SI); in libdw__arch_set_initial_registers()
28 dwarf_regs[7] = REG(DI); in libdw__arch_set_initial_registers()
29 dwarf_regs[8] = REG(IP); in libdw__arch_set_initial_registers()
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/Linux-v4.19/drivers/regulator/
Drn5t618-regulator.c31 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
51 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
52 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
53 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
54 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
56 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
57 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
58 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
59 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
60 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
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/Linux-v4.19/drivers/gpu/drm/amd/display/dc/gpio/dce120/
Dhw_translate_dce120.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
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/Linux-v4.19/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_translate_dcn10.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
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/Linux-v4.19/tools/perf/arch/arm/util/
Dunwind-libdw.c13 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
19 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
20 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
21 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
22 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
23 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
24 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
25 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
26 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
27 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
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/Linux-v4.19/arch/m68k/lib/
Dmulsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
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Dmodsi3.S63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
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Dumodsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
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Ddivsi3.S63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
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Dudivsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
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/Linux-v4.19/arch/sparc/include/asm/
Dtrap_block.h118 #define __GET_CPUID(REG) \ argument
120 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
121 srlx REG, 17, REG; \
122 and REG, 0x1f, REG; \
128 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
129 srlx REG, 17, REG; \
130 and REG, 0x3ff, REG; \
133 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
134 srlx REG, 17, REG; \
135 and REG, 0x1f, REG; \
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Dasm.h14 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
15 brz,PREDICT REG, DEST
16 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
17 brz,a,PREDICT REG, DEST
18 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
19 brnz,PREDICT REG, DEST
20 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
21 brnz,a,PREDICT REG, DEST
27 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
28 cmp REG, 0; \
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c42 #define REG(reg)\ macro
156 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
157 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
166 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in program_gamut_remap()
167 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in program_gamut_remap()
176 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in program_gamut_remap()
177 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in program_gamut_remap()
251 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12); in dpp1_cm_program_color_matrix()
252 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34); in dpp1_cm_program_color_matrix()
256 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in dpp1_cm_program_color_matrix()
[all …]
/Linux-v4.19/arch/mips/ar7/
Dirq.c46 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) macro
55 REG(ESR_OFFSET(d->irq - ar7_irq_base))); in ar7_unmask_irq()
61 REG(ECR_OFFSET(d->irq - ar7_irq_base))); in ar7_mask_irq()
67 REG(CR_OFFSET(d->irq - ar7_irq_base))); in ar7_ack_irq()
72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq()
77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq()
82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq()
111 writel(0xffffffff, REG(ECR_OFFSET(0))); in ar7_irq_init()
112 writel(0xff, REG(ECR_OFFSET(32))); in ar7_irq_init()
113 writel(0xffffffff, REG(SEC_ECR_OFFSET)); in ar7_irq_init()
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/Linux-v4.19/drivers/gpu/drm/i2c/
Dtda998x_drv.c94 #define REG(page, addr) (((page) << 8) | (addr)) macro
102 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
103 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
110 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
111 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
114 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
115 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
116 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
120 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
124 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
[all …]
/Linux-v4.19/arch/arm/mach-netx/include/mach/
Duncompress.h29 #define REG(x) (*(volatile unsigned long *)(x)) macro
47 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) in putc()
49 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) in putc()
54 while (REG(base + UART_FR) & FR_TXFF); in putc()
55 REG(base + UART_DR) = c; in putc()
62 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) in flush()
64 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) in flush()
69 while (REG(base + UART_FR) & FR_BUSY); in flush()
/Linux-v4.19/arch/arm64/kernel/
Dhw_breakpoint.c70 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ argument
72 AARCH64_DBG_READ(N, REG, VAL); \
75 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ argument
77 AARCH64_DBG_WRITE(N, REG, VAL); \
80 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ argument
81 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
82 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
83 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
84 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
85 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
[all …]
/Linux-v4.19/drivers/watchdog/
Dit87_wdt.c48 #define REG 0x2e macro
116 if (!request_muxed_region(REG, 2, WATCHDOG_NAME)) in superio_enter()
119 outb(0x87, REG); in superio_enter()
120 outb(0x01, REG); in superio_enter()
121 outb(0x55, REG); in superio_enter()
122 outb(0x55, REG); in superio_enter()
128 outb(0x02, REG); in superio_exit()
130 release_region(REG, 2); in superio_exit()
135 outb(LDNREG, REG); in superio_select()
141 outb(reg, REG); in superio_inb()
[all …]
Dit8712f_wdt.c61 #define REG 0x2e /* The register to read/write */ macro
99 outb(reg, REG); in superio_inb()
105 outb(reg, REG); in superio_outb()
112 outb(reg++, REG); in superio_inw()
114 outb(reg, REG); in superio_inw()
121 outb(LDN, REG); in superio_select()
130 if (!request_muxed_region(REG, 2, NAME)) in superio_enter()
133 outb(0x87, REG); in superio_enter()
134 outb(0x01, REG); in superio_enter()
135 outb(0x55, REG); in superio_enter()
[all …]
/Linux-v4.19/drivers/gpio/
Dgpio-it87.c49 #define REG 0x2e macro
94 if (!request_muxed_region(REG, 2, KBUILD_MODNAME)) in superio_enter()
97 outb(0x87, REG); in superio_enter()
98 outb(0x01, REG); in superio_enter()
99 outb(0x55, REG); in superio_enter()
100 outb(0x55, REG); in superio_enter()
106 outb(0x02, REG); in superio_exit()
108 release_region(REG, 2); in superio_exit()
113 outb(LDNREG, REG); in superio_select()
119 outb(reg, REG); in superio_inb()
[all …]

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