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/Linux-v4.19/Documentation/PCI/
DPCIEBUS-HOWTO.txt1 The PCI Express Port Bus Driver Guide HOWTO
7 This guide describes the basics of the PCI Express Port Bus driver
9 register/unregister with the PCI Express Port Bus Driver.
13 3. What is the PCI Express Port Bus Driver
15 A PCI Express Port is a logical PCI-PCI Bridge structure. There
16 are two types of PCI Express Port: the Root Port and the Switch
17 Port. The Root Port originates a PCI Express link from a PCI Express
18 Root Complex and the Switch Port connects PCI Express links to
19 internal logical PCI buses. The Switch Port, which has its secondary
21 switch's Upstream Port. The switch's Downstream Port is bridging from
[all …]
/Linux-v4.19/arch/arm/boot/dts/
Darmada-xp-mv78460.dtsi82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
86 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
87 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
88 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
89 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
90 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
91 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
[all …]
Darmada-xp-mv78260.dtsi65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
[all …]
Darmada-xp-mv78230.dtsi64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
[all …]
Darmada-385.dtsi52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
56 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
57 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
58 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
59 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
Darmada-380.dtsi53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
55 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
57 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
58 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
Darmada-xp-db.dts190 /* Port 0, Lane 0 */
194 /* Port 0, Lane 1 */
198 /* Port 0, Lane 2 */
202 /* Port 0, Lane 3 */
206 /* Port 2, Lane 0 */
210 /* Port 3, Lane 0 */
Dkirkwood-6282.dtsi18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
/Linux-v4.19/drivers/usb/serial/
Dio_ionsp.h124 #define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78))… argument
125 #define IOSP_BUILD_DATA_HDR2(Port, Len) ((__u8) (Len)) argument
131 #define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3))… argument
193 #define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \ argument
195 (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), \
203 #define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \ argument
205 (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD); \
/Linux-v4.19/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
99 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
100 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
101 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
102 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
103 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
104 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
105 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
106 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
[all …]
/Linux-v4.19/drivers/isdn/hardware/eicon/
Dio.c667 byte __iomem *Port = DIVA_OS_MEM_ATTACH_PORT((PISDN_ADAPTER)a->io); in io_in() local
668 outppw(Port + 4, (word)(unsigned long)adr); in io_in()
669 val = inpp(Port); in io_in()
670 DIVA_OS_MEM_DETACH_PORT((PISDN_ADAPTER)a->io, Port); in io_in()
676 byte __iomem *Port = DIVA_OS_MEM_ATTACH_PORT((PISDN_ADAPTER)a->io); in io_inw() local
677 outppw(Port + 4, (word)(unsigned long)adr); in io_inw()
678 val = inppw(Port); in io_inw()
679 DIVA_OS_MEM_DETACH_PORT((PISDN_ADAPTER)a->io, Port); in io_inw()
684 byte __iomem *Port = DIVA_OS_MEM_ATTACH_PORT((PISDN_ADAPTER)a->io); in io_in_buffer() local
687 outppw(Port + 4, (word)(unsigned long)adr); in io_in_buffer()
[all …]
Dos_bri.c521 byte __iomem *Port; in diva_bri_reset_adapter() local
532 Port = DIVA_OS_MEM_ATTACH_PORT(IoAdapter); in diva_bri_reset_adapter()
533 addrHi = Port + in diva_bri_reset_adapter()
535 addrLo = Port + ADDR; in diva_bri_reset_adapter()
536 ioaddr = Port + DATA; in diva_bri_reset_adapter()
569 DIVA_OS_MEM_DETACH_PORT(IoAdapter, Port); in diva_bri_reset_adapter()
609 byte __iomem *Port; in diva_bri_write_sdram_block() local
615 Port = DIVA_OS_MEM_ATTACH_PORT(IoAdapter); in diva_bri_write_sdram_block()
616 addrHi = Port + in diva_bri_write_sdram_block()
618 addrLo = Port + ADDR; in diva_bri_write_sdram_block()
[all …]
Ds_bri.c48 byte __iomem *Port; in bri_cpu_trapped() local
54 Port = DIVA_OS_MEM_ATTACH_PORT(IoAdapter); in bri_cpu_trapped()
55 addrHi = Port + ((IoAdapter->Properties.Bus == BUS_PCI) ? M_PCI_ADDRH : ADDRH); in bri_cpu_trapped()
56 addrLo = Port + ADDR; in bri_cpu_trapped()
57 ioaddr = Port + DATA; in bri_cpu_trapped()
99 DIVA_OS_MEM_DETACH_PORT(IoAdapter, Port); in bri_cpu_trapped()
/Linux-v4.19/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
[all …]
/Linux-v4.19/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dts194 reg = <0x3>; /* Port */
201 reg = <0x4>; /* Port */
206 reg = <0x5>; /* Port */
211 reg = <0x6>; /* Port */
216 reg = <0x7>; /* Port */
221 reg = <0x8>; /* Port */
226 reg = <0x9>; /* Port */
231 reg = <0xa>; /* Port */
236 reg = <0xb>; /* Port */
241 reg = <0xc>; /* Port */
[all …]
Docteon_68xx.dts269 reg = <0x0>; /* Port */
275 reg = <0x1>; /* Port */
281 reg = <0x2>; /* Port */
287 reg = <0x3>; /* Port */
301 reg = <0x0>; /* Port */
307 reg = <0x1>; /* Port */
313 reg = <0x2>; /* Port */
319 reg = <0x3>; /* Port */
333 reg = <0x0>; /* Port */
339 reg = <0x1>; /* Port */
[all …]
/Linux-v4.19/Documentation/s390/
Dqeth.txt3 OSA and HiperSockets Bridge Port Support
8 a primary or a secondary Bridge Port. For more information, see
11 When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state
12 of some configured Bridge Port device on the channel changes, a udev
16 BRIDGEPORT=statechange - indicates that the Bridge Port device changed
23 When run on HiperSockets Bridge Capable Port hardware with host address
31 deregistered on the Bridge Port HiperSockets channel, or address
/Linux-v4.19/Documentation/devicetree/bindings/display/msm/
Dmdp5.txt63 Port 0 -> MDP_INTF0 (eDP)
64 Port 1 -> MDP_INTF1 (DSI1)
65 Port 2 -> MDP_INTF2 (DSI2)
66 Port 3 -> MDP_INTF3 (HDMI)
69 Port 0 -> MDP_INTF1 (DSI1)
72 Port 0 -> MDP_INTF1 (DSI1)
73 Port 1 -> MDP_INTF2 (DSI2)
74 Port 2 -> MDP_INTF3 (HDMI)
Dmdp4.txt33 Port 0 -> LCDC/LVDS
34 Port 1 -> DSI1 Cmd/Video
35 Port 2 -> DSI2 Cmd/Video
36 Port 3 -> DTV
/Linux-v4.19/drivers/usb/typec/
DKconfig26 Simple USB Type-C PHYs, for example USB Type-C Port Controller
27 Interface Specification compliant "Port Controllers" need the state
49 tristate "USB Type-C Port Controller Manager"
54 The Type-C Port Controller Manager provides a USB PD and USB Type-C
55 state machine for use with Type-C Port Controllers.
60 tristate "Type-C Port Controller Interface driver"
64 Type-C Port Controller driver for TCPCI-compliant controller.
72 Type-C Port Controller Manager to provide USB PD and USB
/Linux-v4.19/drivers/pci/pcie/
DKconfig3 # PCI Express Port Bus Configuration
6 bool "PCI Express Port Bus support"
9 This automatically enables PCI Express Port Bus support. Users can
32 This enables PCI Express Root Port Advanced Error Reporting
34 Port will be handled by PCI Express AER driver.
41 This enables PCI Express Root Port Advanced Error Reporting
130 bool "PCI Express Downstream Port Containment support"
134 This enables PCI Express Downstream Port Containment (DPC)
/Linux-v4.19/Documentation/devicetree/bindings/net/
Dcavium-pip.txt62 reg = <0x0>; /* Port */
68 reg = <0x1>; /* Port */
74 reg = <0x2>; /* Port */
80 reg = <0x3>; /* Port */
94 reg = <0x0>; /* Port */
Dcortina,gemini-ethernet.txt69 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
70 <0x6000a000 0x2000>; /* Port 0 GMAC */
82 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
83 <0x6000e000 0x2000>; /* Port 1 GMAC */
/Linux-v4.19/arch/arc/boot/dts/
Dabilis_tb100.dtsi42 /* Port 1 */
55 /* Port 2 */
68 /* Port 3 */
81 /* Port 4 */
94 /* Port 5 */
107 /* Port 6 */
123 /* Port 7 */
136 /* Port 8 */
140 /* Port 9 */
Dabilis_tb101.dtsi42 /* Port 1 */
55 /* Port 2 */
68 /* Port 3 */
81 /* Port 4 */
94 /* Port 5 */
113 /* Port 6 */
129 /* Port 7 */
142 /* Port 8 */
149 /* Port 9 */

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